• 한국초전도저온공학회:학술대회논문집
• /
• 한국초전도저온공학회 2003년도 추계학술대회 논문집
• /
• pp.153-156
• /
• 2003

The multi-layer oxide buffer layer for the coated conductor was deposited on biaxially textured Ni substrates using pulsed laser deposition. Oxygen partial pressure, 4％$H_2$/Ar partial pressure, and deposition temperature were deposition variables investigated to find the optimum deposition conditions. $Y_2$O$_3$seed layer was deposited epitaxially on metal substrate. The full buffer architecture of $Y_2$O$_3$/YSZ/CeO$_2$was successfully prepared on metal substrate.

• 한국재료학회지
• /
• 제12권5호
• /
• pp.327-333
• /
• 2002

In order to obtain the oxidation layer for SiC MOS, the oxide layers by thermal oxidation process with dry and wet method were deposited and characterized. Deposition temperature for oxidation layer was $1100^{\circ}C$~130$0^{\circ}C$ by $O_2$ and Ar atmosphere. The oxide thickness, surface morphology, and interface characteristic of deposited oxide layers were measurement by ellipsometer, SEM, TEM, AFM, and SIMS. Thickness of oxidation layer was confirmed 50nm and 90nm to with deposition temperature at $1150^{\circ}C$ and $1200{\circ}C$ for dry 4 hours and wet 1 hour, respectively. For the high purity oxidation layer, the necessity of sacrificial oxidation which is etched for the removal of the defeats on the wafer after quickly thermal oxidation was confirmed.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
• /
• pp.1414-1415
• /
• 2006

Air-gap type film bulk acoustic wave resonator device using ZnO for piezoelectric layer and sacrifice layer, deposited by RF magnetron sputter with various conditions, fabricated in this study. Also, membrane$(SiO_2)$ and top and bottom electrode(both Al) of piezoelectric layer deposited by RF magnetron sputter. Using micro electro mechanical systems(MEMS) technique, sacrifice layer removed and then air-gap formed. The results of each process checked by XRD, AFM, SEM to obtain good quality device.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
• /
• pp.237.2-237.2
• /
• 2016

A pure hafnium-carbide (HfC) coating layer was deposited onto carbon/carbon (C.C) composites using a vacuum plasma spray system. By adopting a SiC buffer layer, we successfully integrated C.C composites with a $100-{\mu}m-thick$ protective coating layer of HfC. Compared to the conventional chemical vapor deposition process, the HfC coating process by VPS showed increased growth rate, thickness, and hardness. The growth behavior and morphology of HfC coatings were investigated by FE-SEM, EDX, and XRD. From these results, it was shown that the addition of a SiC intermediate layer provided optimal surface conditions during the VPS procedure to enhance adhesion between C.C and HfC (without delamination). The thermal ablation test results shows that the HfC coating layer perfectly protected inner C.C layer from thermal ablation and oxidation. Consequently, we expect that this ultra-high temperature ceramic coating method, and the subsequent microstructure that it creates, can be widely applied to improve the thermal shock and oxidation resistance of materials under ultra-high temperature environments.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1996년도 추계학술대회 논문집
• /
• pp.242-244
• /
• 1996

The effects of $Co_{67}$C $r_{33}$ underlayer on the crystallographec and magnetic characteristics of the Co-Cr-Ta layer deposited on the underlayer was investigated. The diffraction intensity $I_{p(002)}$ of Co-Cr-Ta layers on the $Co_{67}$C $r_{33}$ layer was stronger than that of single layer and Co-Cr-Ta/Ti double layer. Therefore, the crystallinity of Co-Cr-Ta layer was improved by the $Co_{67}$C $r_{33}$ underlayers rather than Ti ones. However, the coercivity $H_{c}$ of Co-Cr-Ta layers deposited on $Co_{67}$C $r_{33}$ underlayer was as low as 250 Oe even at substrate temperature of 22$0^{\circ}C$. This $H_{c}$ decrease seems to be attributed to the effect of the $Co_{67}$C $r_{33}$ underlayer as well as interval time between deposition of the underlayer and the Co-Cr-Ta layer.yer.layer.yer.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
• /
• pp.299.2-299.2
• /
• 2013

We investigated the potassium remaining on a crystalline silicon solar cell after potassium hydroxide (KOH) etching and its effect on the lifetime of the solar cell. KOH etching is generally used to remove the saw damage caused by cutting a Si ingot; it can also be used to etch the rear side of a textured crystalline silicon solar cell before atomic layer-deposited Al2O3 growth. However, the potassium remaining after KOH etching is known to be detrimental to the efficiency of Si solar cells. In this study, we etched a crystalline silicon solar cell in three ways in order to determine the effect of the potassium remnant on the efficiency of Si solar cells. After KOH etching, KOH and tetramethylammonium hydroxide (TMAH) were used to etch the rear side of a crystalline silicon solar cell. To passivate the rear side, an Al2O3 layer was deposited by atomic layer deposition (ALD). After ALD Al2O3 growth on the KOH-etched Si surface, we measured the lifetime of the solar cell by quasi steady-state photoconductance (QSSPC, Sinton WCT-120) to analyze how effectively the Al2O3 layer passivated the interface of the Al2O3 layer and the Si surface. Secondary ion mass spectroscopy (SIMS) was also used to measure how much potassium remained on the surface of the Si wafer and at the interface of the Al2O3 layer and the Si surface after KOH etching and wet cleaning.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2011년도 제40회 동계학술대회 초록집
• /
• pp.204-205
• /
• 2011

In thin film silicon solar cells, p-i-n structure is adopted instead of p/n junction structure as in wafer-based Si solar cells. PECVD is a most widely used thin film deposition process for a-Si:H or ${\mu}c$-Si:H solar cells. For best performance of thin film silicon solar cell, the dopant profiles at p/i and i/n interfaces need to be as sharp as possible. The sharpness of dopant profiles can easily achieved when using multi-chamber PECVD equipment, in which each layer is deposited in separate chamber. However, in a single-chamber PECVD system, doped and intrinsic layers are deposited in one plasma chamber, which inevitably impedes sharp dopant profiles at the interfaces due to the contamination from previous deposition process. The cross-contamination between layers is a serious drawback of a single-chamber PECVD system in spite of the advantage of lower initial investment cost for the equipment. In order to resolve the cross-contamination problem in single-chamber PECVD systems, flushing method of the chamber with NH3 gas or water vapor after doped layer deposition process has been used. In this study, a new plasma process to solve the cross-contamination problem in a single-chamber PECVD system was suggested. A single-chamber VHF-PECVD system was used for superstrate type p-i-n a-Si:H solar cell manufacturing on Asahi-type U FTO glass. A 80 MHz and 20 watts of pulsed RF power was applied to the parallel plate RF cathode at the frequency of 10 kHz and 80% duty ratio. A mixture gas of Ar, H2 and SiH4 was used for i-layer deposition and the deposition pressure was 0.4 Torr. For p and n layer deposition, B2H6 and PH3 was used as doping gas, respectively. The deposition temperature was $250^{\circ}C$ and the total p-i-n layer thickness was about $3500{\AA}$. In order to remove the deposited B inside of the vacuum chamber during p-layer deposition, a high pulsed RF power of about 80 W was applied right after p-layer deposition without SiH4 gas, which is followed by i-layer and n-layer deposition. Finally, Ag was deposited as top electrode. The best initial solar cell efficiency of 9.5 % for test cell area of 0.2 $cm^2$ could be achieved by applying the in-situ plasma cleaning method. The dependence on RF power and treatment time was investigated along with the SIMS analysis of the p-i interface for boron profiles.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.154-154
• /
• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2011년도 제40회 동계학술대회 초록집
• /
• pp.479-479
• /
• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Current Photovoltaic Research
• /
• 제8권2호
• /
• pp.45-49
• /
• 2020

Molybdenum (Mo) thin films are widely used as back contact in copper indium diselenide (CISe) solar cells. However, despite this, there are only few published studies on the properties of Mo and characteristics of CISe solar cells formed on such Mo substrates. In this studies, we investigated the properties of sputter deposited Mo bilayer, and fabricated non-vacuum CISe solar cells using bilayer Mo substrates. The changes in surface morphology and electrical resistivity were traced by varying the gas pressure during deposition of the bottom Mo layer. In porous surface structure, it was confirmed that the electrical resistivity of Mo bilayer was increased as the amount of oxygen bonded to the Mo atoms increased. The resulting solar cell characteristics vary as the bottom Mo layer deposition pressure, and the maximum solar cell efficiency was achieved when the bottom layer was deposited at 7 mTorr with a thickness of 100 nm and the top layer deposited at 3 mTorr with a thickness of 400 nm.