• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.135-141
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• 2020

Today, CPUs in general-purpose computers such as servers, desktops and laptops, as well as home appliances and embedded systems, consist mostly of multicore processors. In order to improve performance, it is required to use an out-of-order execution processor by Tomasulo algorithm as each core processor. An out-of-order execution processor with Tomasulo algorithm can execute the available instructions in any order and perform speculation in order to reduce control dependencies. Therefore, the performance of an out-of-order execution processor can be significantly improved compared to an in-order execution processor. In this paper, an out-of-order execution processor using Tomasulo algorithm and ARM instruction set is designed using VHDL record data types and simulated by GHDL. As a result, it is possible to successfully perform operations on programs written in ARM instructions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1076-1085
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• 2004

Recently, the demands for real-time service and multimedia data are rapidly increasing. There are significant redundancies between header fields both within the same packet header and in consecutive packets belonging to the same packet stream. And there are many overheads in using the current UDP/IP protocol. Header compression is considered to enhance the transmission efficiency for the payload of small size. By sending the static field information only once initially and by utilizing dependencies and predictability for other fields, the header size can be significantly reduced for most packets. This work describes an implementation for header compression of the headers of IP/UDP protocols to reduce the overhead on Ethernet network. Typical UDP/IP Header packets can be compressed down to 7 bytes and the header compression system is designed and implemented in Linux environment. Using the Header compression system designed between a server and clients provides have the advantage of effective data throughput in network. Since the minimum packet size in Ethernet is 64 bytes, the amount of reduction by header compression in practical chatting environment was 6.6 bytes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.400-403
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• 2018

The VR / AR market has grown significantly due to the development of Virtual Reality and Augmented Reality, the core technologies of the Fourth Industrial Revolution. According to a report released by the Korea Science and Engineering Corporation (KISTEP), the global VR / AR market will grow to $ 105 billion by 2022. An important key to the growth of the VR / AR market is user immersion. VR is dependent on technology of hardware such as display and sensor for biometric signal recognition. In order to improve user's immersion feeling, it is important to transmit sensor data to display device more accurately and quickly. In this paper, we consider various sensor hardware dependencies of VR, and compare various correction methods and filtering methods to lower the Motion to Photon (MTP) time that user movement is fully reflected on the display using sensor devices.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.11
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• pp.383-390
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• 2015

It is appropriate to use the NETCONF to monitor and manage today's complex networks that are composed of variety links and heterogeneous equipment. Since the first standard of the NETCONF are launched, there have been several revisions, but disadvantages of each layer capabilities is still present and the most typical disadvantage is XML document processing efficiency of the Content layer. In this paper, we perform data modeling by constructing a sub-tree based on the dependencies between Content layer data, and suggest method of extract efficiently data from XML by applying the extended VTD-XML technique for the XPath query. We performs experiment to compare NETCONF in proposed method to NETCONF in previous studies and NETCONF standard. we validate superiority of improved NETCONF in the paper. As experimental results, we verify that improved NETCONF is better than the other two NETCONF each 4% and 10% in terms of query processing rate, and faster than each 3.9 seconds and 10.4 seconds in terms of query processing speed.

• The KIPS Transactions:PartD
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• v.15D no.4
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• pp.495-504
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• 2008

Aspect Oriented Programming(AOP) is a relatively new programming paradigm and has properties that other programming paradigms don't have. This new programming paradigm provides new modularization of software systems by cross-cutting concerns. In this paper, we propose a regression test method for program evolution by AOP. By using JoinPoint, we can catch a pointcut-name which makes it possible to test the incorrect pointcut strength fault and the incorrect aspect precedence fault. Through extending proof rules to aspect, we can recognize failures to establish expected postconditions faults. We can also trace variables using set() and get() pointcut and test failures to preserve state invariant fault. Using control flow graph, we can test incorrect changes in control dependencies faults. In order to show the correctness of our proposed method, channel management system is implemented and tested by using proposed methods.

• KIPS Transactions on Software and Data Engineering
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• v.3 no.1
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• pp.43-48
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• 2014

Usually, image deconvolution is applied as a preprocessing step in surveillance systems to reduce the effect of motion or out-of-focus blur problem. In this paper, we propose a blind-image deconvolution filtering approach based on genetic programming (GP). A numerical expression is developed using GP process for image restoration which optimally combines and exploits dependencies among features of the blurred image. In order to develop such function, first, a set of feature vectors is formed by considering a small neighborhood around each pixel. At second stage, the estimator is trained and developed through GP process that automatically selects and combines the useful feature information under a fitness criterion. The developed function is then applied to estimate the image pixel intensity of the degraded image. The performance of developed function is estimated using various degraded image sequences. Our comparative analysis highlights the effectiveness of the proposed filter.

• Journal of the Korean Magnetics Society
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• v.8 no.3
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• pp.118-124
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• 1998

$Ni_{0.65}Zn_{0.35}Cu_{0.1}Fe{1.9}O_4$ has been studied with Mossbauer spectroscopy and X-ray diffraction. The crystal structure is found to be a cubic spinel with the lattice constant $a_0=8.390{\AA}$. Mossbauer spectra of $Ni_{0.65}Zn_{0.35}Cu_{0.1}Fe{1.9}O_4$ has been taken at various temperatures ranging from 12 K to 705 K. The isomer shift indicates that iron ions are ferric at tetrahedral [A] and octahedral sites [B], respectively. The Neel temperature is determined to be $T_N=705\;K$. As the temperature increases toward $T_N$ a systematic line broadening effect in the Mossbauer spectrum is observed and interpreted to originate from different temperature dependencies of the magnetic hyperfine fields at various iron sites. The quadrupole splitting just on $T_N$ is 0.41 mm/s whereas the quadrupole shift below $T_N$ vanishes. This implies that the orientation of the magnetic hyperfine field with respect to be principal axes of the electric field gradient is random.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.2 s.314
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• pp.1-10
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• 2007

Branch prediction accuracy is critical for the overall system performance. Branch miss-prediction penalty is the one of the significant performance limiters for improving processor performance, as the pipeline deepens and the instruction issued per cycle increases. In this paper, we propose "Dynamic Per-Branch History Length Fitting Method" by tracking the data dependencies among the register writing instructions. The proposed solution first identifies the key branches, and then it selectively uses the histories of the key branches. To support this mechanism, we provide a history length adjustment algorithm and a required hardware module. As the result of simulation, the proposed mechanism outperforms the previous fixed static method, up to 5.96% in prediction accuracy. Furthermore, our method introduces the performance improvement, compared to the profiled results which are generally considered as the optimal ones.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.172-180
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• 2003

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/40 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.

• Aerospace Engineering and Technology
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• v.10 no.2
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• pp.105-113
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• 2011

During the development of flight software, the processor emulator and satellite simulator are essential tools for software development and verification, which can be substituted for the actual hardware. LEO satellites being developed by KARI recently use the MCM-ERC32SC processor for on-board computer (OBC). For the flight software (FSW) development and testing, the software-based spacecraft simulator was developed using TSIM-ERC32 processor emulator from Aeroflex Gaisler. It is needed to get rid of the constraints and dependencies of TSIM-ERC32 processor emulator and to obtain high performance processor emulator to develop full satellite simulator. This paper presents the development of the ERC32 emulator based on open source dynamic translator, QEMU, as the first step. And it describes the software development and testing/debugging on the developed emulator.