• Smart Structures and Systems
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• 제14권6호
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• pp.1247-1267
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• 2014

Real-Time Hybrid Simulation (RTHS) is a novel approach conceived to evaluate dynamic responses of structures with parts of a structure physically tested and the remainder parts numerically modelled. In RTHS, delay estimation is often a precondition of compensation; nonetheless, system delay may vary during testing. Consequently, it is sometimes necessary to measure delay online. Along these lines, this paper proposes an online delay estimation method using least-squares algorithm based on a simplified physical system model, i.e., a pure delay multiplied by a gain reflecting amplitude errors of physical system control. Advantages and disadvantages of different delay estimation methods based on this simplified model are firstly discussed. Subsequently, it introduces the least-squares algorithm in order to render the estimator based on Taylor series more practical yet effective. As a result, relevant parameter choice results to be quite easy. Finally in order to verify performance of the proposed method, numerical simulations and RTHS with a buckling-restrained brace specimen are carried out. Relevant results show that the proposed technique is endowed with good convergence speed and accuracy, even when measurement noises and amplitude errors of actuator control are present.

• Genomics & Informatics
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• 제15권3호
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• pp.82-86
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• 2017

Chromosomal microarray (CMA) is a high-resolution, high-throughput method of identifying submicroscopic genomic copy number variations (CNVs). CMA has been established as the first-line diagnostic test for individuals with developmental delay (DD), intellectual disability (ID), autism spectrum disorders (ASDs), and multiple congenital anomalies (MCAs). CMA analysis was performed in 42 Korean patients who had been diagnosed with unexplained DD, ID, ASDs, and MCAs. Clinically relevant CNVs were discovered in 28 patients. Variants of unknown significance were detected in 13 patients. The diagnostic yield was high (66.7%). CMA is a superior diagnostic tool compared with conventional karyotyping and fluorescent in situ hybridization.

• 대한전자공학회논문지SD
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• 제38권10호
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• pp.728-734
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• 2001

현재의 IEEE 1149.1 바운다리스캔 표준안은 보드나 내장 코어의 연결선상의 지연고장은 점검 할 수 없다. 본 논문에서는 표준안에 위배기지 않게 TAP 제어기를 수정함으로 시스템 클럭 속도에서 지연고장을 점검 할 수 있는 기술을 개발하였다. 실험을 통해서 본 논문에서 제안한 방법이 기존의 방법보다 추가되는 면적이 적음을 보였다.

• 한국정보시스템학회지:정보시스템연구
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• 제8권1호
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• pp.93-108
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• 1999

The switching system is designed and developed to satisfy the performance design objectives recommended by ITU for call processing capacity and quality of service(QOS), etc. When the results by actual measurement at the system testing phase do not satisfy the performance design objectives, however, an effort is required to improve the performance. This paper presents a method for improving QOS by modifying the application programs for the switching system. In the proposed method, the sequence chart related to a delay time for call connection is modelled using PERT(Program Evaluation and Review Technique) network. Then, the criticality index of a message is calculated using Monte Carlo simulation to evaluate which message's processing time to decrease in order to decrease the delay time and thus to improve QOS. The criticality index of a block is also calculated to identify those software blocks that significantly contribute to the delay time.

• Smart Structures and Systems
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• 제14권6호
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• pp.1005-1030
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• 2014

The need for assessing dynamic response of typical industrial piping systems subjected to seismic loading motivated the authors to apply model reduction techniques to experimental dynamic substructuring. Initially, a better insight into the dynamic response of the emulated system was provided by means of the principal component analysis. The clear understanding of reduction basis requirements paved the way for the implementation of a number of model reduction techniques aimed at extending the applicability range of the hybrid testing technique beyond its traditional scope. Therefore, several hybrid simulations were performed on a typical full-scale industrial piping system endowed with a number of critical components, like elbows, Tee joints and bolted flange joints, ranging from operational to collapse limit states. Then, the favourable performance of the L-Stable Real-Time compatible time integrator and an effective delay compensation method were also checked throughout the testing campaign. Finally, several aspects of the piping performance were commented and conclusions drawn.

• 전자공학회논문지B
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• 제32B권11호
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• 한국정밀공학회지
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• 제15권6호
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• pp.167-174
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• 1998

The ultrasonic test is recognized for its significance as a non-destructive testing method to detect volume defects such as porosity and incomplete penetration which reduce strength in the weld zone. This paper illustrates the defect detection in the weld zone of ferritic carbon steel using ultrasonic wave and the evaluation of pattern recognition by chaotic feature extraction using time series signal of detected defects as data. Shown in the time series data were that the time delay was 4 and the embedding dimension was 6 which indicate the geometric dimension of the subject system and the extent of information correlation. Based on fractal dimension and lyapunov exponent in quantitative chaotic feature extraction, feature value of 2.15, 0.47 is presented for porosity and 2.24, 0.51 for incomplete penetration The precision rate of the pattern recognition is enhanced with these values on the total waveform of defect signal in the weld zone. Therefore, we think that the ultrasonic pattern recognition method of weld zone defects of ferritic carbon steel by ultrasonic-chaotic feature extraction proposed in this paper can boost precision rate further than the existing method applying only partial waveform.

• Journal of Positioning, Navigation, and Timing
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• 제12권3호
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• pp.237-244
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• 2023

A signal generation simulator is an economical and useful solution in Global Navigation Satellite System (GNSS) receiver design and testing. A software-defined radio approach is widely used both in receivers and simulators, and its flexible structure to adopt to new signals is ideally suited to the testing of a receiver and signal processing algorithm in the signal design phase of a new satellite-based navigation system before the deployment of satellites in space. The generation of highly accurate delayed sampled codes is essential for generating signals in the simulator, where its sampling rate should be chosen to satisfy constraints such as Nyquist criteria and integer and non-commensurate properties in order not to cause any distortion of original signals. A high sampling rate increases the accuracy of code delay, but decreases the computational efficiency as well, and vice versa. Therefore, the selected sampling rate should be as low as possible while maintaining a certain level of code delay accuracy. This paper presents the lower limits of the sampling rate for GNSS signal generation simulators. In the simulation, two distinct code generation methods depending on the sampling position are evaluated in terms of accuracy versus computational efficiency to show the lower limit of the sampling rate for several GNSS signals.

• 한국음향학회지
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• 제22권2호
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• pp.153-161
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• 2003

본 논문에서는 음파가 다중 경로를 통하여 수신되는 경우 음파의 도달시간을 보다 정확하게 파악하기 위한 방법으로 웨이브렛 패킷을 기반으로 한 신호 처리 기법을 제안하였다. 그 식별 성능 분석을 위해 제안된 방법과 기존의 정합 필터 방법을 모의 실험하였고, 또한 실측 신호에 대해 적용하여 비교 및 분석하였다. 그 결과 제안된 웨이브렛 패킷 기반의 신호처리 방법이 정합 필터 방법을 적용한 경우보다 많은 도달 시간을 식별하였고, 기존의 정합 필터 방법으로 식별하기 어려운 다중경로 환경에서의 도달시간을 보다 효율적으로 추정할 수 있는 가능성을 확인하게 되었다.