• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1161-1166
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• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.266-276
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• 2001

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has heavily increased. With the increased densities of integrated circuits, several different types of faults can occur Thus, testing such circuits is becoming a sever problem. Delay testing can detect system timing failures caused by delay faults. However, the conventional delay fault coverage in terms of the number of detected faults may not be an effective measure of delay testing because, unlike a stuck-at-faults, the impact of a delay fault is dependent on its delay defect size rather than on its existence. Thus, the effectiveness of delay testing is dependent on the propagation delay of the path to be tested, the delay defect size, and the system clock interval. This paper proposes a new delay defect fault coverage that considers both propagation delay of the path to be tested and additional delay defect size. And the relationship between delay defect fault coverage and defect level is analyzed.

• Smart Structures and Systems
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• v.4 no.6
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• pp.809-828
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• 2008

Real-time hybrid testing is an attractive method to evaluate the response of structures under earthquake loads. The method is a variation of the pseudodynamic testing technique in which the experiment is executed in real time, thus allowing investigation of structural systems with time-dependent components. Real-time hybrid testing is challenging because it requires performance of all calculations, application of displacements, and acquisition of measured forces, within a very small increment of time. Furthermore, unless appropriate compensation for time delays and actuator time lag is implemented, stability problems are likely to occur during the experiment. This paper presents an approach for real-time hybrid testing in which time delay/lag compensation is implemented using model-based response prediction. The efficacy of the proposed strategy is verified by conducting substructure real-time hybrid testing of a steel frame under earthquake loads. For the initial set of experiments, a specimen with linear-elastic behavior is used. Experimental results agree well with the analytical solution and show that the proposed approach and testing system are capable of achieving a time-scale expansion factor of one (i.e., real time). Additionally, the proposed method allows accurate testing of structures with larger frequencies than when using conventional time delay compensation methods, thus extending the capabilities of the real-time hybrid testing technique. The method is then used to test a structure with a rate-dependent energy dissipation device, a magnetorheological damper. Results show good agreement with the predicted responses, demonstrating the effectiveness of the method to test rate-dependent components.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1269-1289
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• 2014

With the sub-stepping technique, the numerical analysis in real-time dynamic hybrid testing is split into the response analysis and signal generation tasks. Two target computers that operate in real-time may be assigned to implement these two tasks, respectively, for fully extending the simulation scale of the numerical substructure. In this case, the integration time-step of solving the dynamic response of the numerical substructure can be dozens of times bigger than the sampling time-step of the controller. The time delay between the real and desired feedback forces becomes more striking, which challenges the well-developed delay compensation methods in real-time dynamic hybrid testing. This paper focuses on displacement prediction and force correction for delay compensation in the real-time dynamic hybrid testing with a large integration time-step. A new displacement prediction scheme is proposed based on recently-developed explicit integration algorithms and compared with several commonly-used prediction procedures. The evaluation of its prediction accuracy is carried out theoretically, numerically and experimentally. Results indicate that the accuracy and effectiveness of the proposed prediction method are of significance.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.14-21
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• 1997

In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the delay-optimized design in order to have the same defect-level for delay faults as the non-optimized design, while the system clock time is the same for both designs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.72-84
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• 2001

The timings of all computational elements in the micropipeline circuits are important. The previous researches on path delay testing using scan methods make little account of the characteristic of the path delay tests that the second test pattern must be more controllable. In this paper, a new scan latch is proposed which is suitable to path delay testing of the micropipelines and has small area overhead. Results show that path delay faults in the micropipeline circuits using the new scan are testable robustly and the fault coverage is higher than the previous researches. In addition, the new scan latch for path delay faults testing in the micropipeline circuits can be easily expanded to the applications such as BIST for stuck-at faults.

• Clinical and Experimental Pediatrics
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• v.63 no.6
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• pp.195-202
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• 2020

Developments in next-generation sequencing (NGS) techogies have assisted in clarifying the diagnosis and treatment of developmental delay/intellectual disability (DD/ID) via molecular genetic testing. Advances in DNA sequencing technology have not only allowed the evolution of targeted panels but also, and more currently enabled genome-wide analyses to progress from research era to clinical practice. Broad acceptance of accuracy-guided targeted gene panel, whole-exome sequencing (WES), and whole-genome sequencing (WGS) for DD/ID need prospective analyses of the increasing cost-effectiveness versus conventional genetic testing. Choosing the appropriate sequencing method requires individual planning. Data are required to guide best-practice recommendations for genomic testing, regarding various clinical phenotypes in an etiologic approach. Targeted panel testing may be recommended as a firsttier testing approach for children with DD/ID. Family-based trio testing by WES/WGS can be used as a second test for DD/ID in undiagnosed children who previously tested negative on a targeted panel. The role of NGS in molecular diagnostics, treatment, prediction of prognosis will continue to increase further in the coming years. Given the rapid pace of changes in the past 10 years, all medical providers should be aware of the changes in the transformative genetics field.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.807-810
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• 1998

This paper presents BIST (Built-in self-test) techniques for detection of path delay faults in digital circuits. In the proosed BIST schemes, the shift registers make possible to concurrently generate and compact the latched test data. Therefore the test time is reduced efficiently. By reordering the elements of th shifte register based on the information of the hamming distance of each memory elements in CUt, it is possible to increase the number of path delay faults detected robustly/non-robustly. Experimental results for ISCAS'89 benchmark circuits show the efficiency of the proposed BIST techniques.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1055-1079
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• 2014

Substructure shake table testing is a class of real-time hybrid simulation (RTHS). It combines shake table tests of substructures with real-time computational simulation of the remaining part of the structure to assess dynamic response of the entire structure. Unlike in the conventional hybrid simulation, substructure shake table testing imposes acceleration compatibilities at substructure boundaries. However, acceleration tracking of shake tables is extremely challenging, and it is not possible to produce perfect acceleration tracking without time delay. If responses of the experimental substructure have high correlation with ground accelerations, response errors are inevitably induced by the erroneous input acceleration. Feeding the erroneous responses into the RTHS procedure will deteriorate the simulation results. This study presents a set of techniques to enable reliable substructure shake table testing. The developed techniques include compensation techniques for errors induced by imperfect input acceleration of shake tables, model-based actuator delay compensation with state observer, and force correction to eliminate process and measurement noises. These techniques are experimentally investigated through RTHS using a uni-axial shake table and three-story steel frame structure at the Johns Hopkins University. The simulation results showed that substructure shake table testing with the developed compensation techniques provides an accurate and reliable means to simulate the dynamic responses of the entire structure under earthquake excitations.

• ETRI Journal
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• v.25 no.3
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• pp.187-194
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• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.