• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1645-1650
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• 2005

FOPDT(First-Order Plus Dead-Time) and SOPDT(Second-Order Plus Dead-Time) process, which are used as the most useful process in industry, are difficult about process identification because of the long dead-time problem and the model mismatch problem. Thus, the accuracy of process identification is the most important problem in FOPDT and SOPDT process control. In this paper, we proposed the real-coded genetic algorithm for identification of FOPDT and SOPDT processes. The proposed method using real-coding genetic algorithm shows better performance characteristic comparing with the existing an area-based identification method and a directed identification method that use step-test responses. The proposed strategy obtained useful result through a number of simulation examples.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.69-72
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• 2001

Blind equalization of transmission channel is important in communication areas and signal processing applications because it does not need training sequence, nor does it require a priori channel information. Recently, Tong et al. proposed solutions for this problem exploit the diversity induced by antenna array or time oversampling, leading to the second order statistics techniques, fur example, subspace method, prediction error method, and so on. The linear prediction error method is perhaps the most attractive in practice due to the insensitive to blind equalizer length mismatch as well as for its simple adaptive filter implementation. Unfortunately, the previous one-step prediction error method is known to be limited in arbitrary delay. In this paper, we induce the optimal delay, and propose the adaptive blind equalizer with multi-step linear prediction using RLS-type algorithm. Simulation results are presented to demonstrate the proposed algorithm and to compare it with existing algorithms.

• ETRI Journal
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• 제38권1호
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• pp.185-194
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• 2016

In this paper, a novel rate control scheme for low delay video coding of High Efficiency Video Coding (HEVC) is proposed. The proposed scheme is developed by considering a new temporal prediction structure of HEVC. In the proposed scheme, the relationship between bit rate and quantization step is exploited firstly to formulate an accurate quadratic rate-quantization (R-Q) model. Secondly, a method of determining the quantization parameters (QPs) for the first frames within a group of pictures is proposed. Thirdly, an accurate frame-level bit allocation method is proposed for HEVC. Finally, based on the proposed R-Q model and the target bit allocated for the frame, the QPs are predicted for coding tree units by using rate-distortion (R-D) optimization. We compare our scheme against that of three other state-of-the-art rate control schemes. Experimental results show that the proposed rate control scheme can increase the Bjøntegaard delta peak signal-to-noise ratio by 0.65 dB and 0.09 dB on average compared with the JCTVC-I0094 and JCTVC-M0036 schemes, respectively, both of which have been implemented in an HEVC test model encoder; furthermore, the proposed scheme achieves a similar R-D performance to Wang's scheme, as well as obtaining the smallest bit rate mismatch error of all the schemes.

• 대한청각학회지
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• 제24권3호
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• pp.119-126
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• 2020

Background and Objectives: In distracting listening conditions, individuals need to pay extra attention to selectively listen to the target sounds. To investigate the amount of listening effort required in reverberating and noisy backgrounds, a semantic mismatch was examined. Subjects and Methods: Electroencephalography was performed in 18 voluntary healthy participants using a 64-channel system to obtain N400 latencies. They were asked to listen to sounds and see letters in 2 reverberated×2 noisy paradigms (i.e., Q-0 ms, Q-2000 ms, 3 dB-0 ms, and 3 dB-2000 ms). With auditory-visual pairings, the participants were required to answer whether the auditory primes and letter targets did or did not match. Results: Q-0 ms revealed the shortest N400 latency, whereas the latency was significantly increased at 3 dB-2000 ms. Further, Q-2000 ms showed approximately a 47 ms delayed latency compared to 3 dB-0 ms. Interestingly, the presence of reverberation significantly increased N400 latencies. Under the distracting conditions, both noise and reverberation involved stronger frontal activation. Conclusions: The current distracting listening conditions could interrupt the semantic mismatch processing in the brain. The presence of reverberation, specifically a 2000 ms delay, necessitates additional mental effort, as evidenced in the delayed N400 latency and the involvement of the frontal sources in this study.

• Journal of Audiology & Otology
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• 제24권3호
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• pp.119-126
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• 2020

Background and Objectives: In distracting listening conditions, individuals need to pay extra attention to selectively listen to the target sounds. To investigate the amount of listening effort required in reverberating and noisy backgrounds, a semantic mismatch was examined. Subjects and Methods: Electroencephalography was performed in 18 voluntary healthy participants using a 64-channel system to obtain N400 latencies. They were asked to listen to sounds and see letters in 2 reverberated×2 noisy paradigms (i.e., Q-0 ms, Q-2000 ms, 3 dB-0 ms, and 3 dB-2000 ms). With auditory-visual pairings, the participants were required to answer whether the auditory primes and letter targets did or did not match. Results: Q-0 ms revealed the shortest N400 latency, whereas the latency was significantly increased at 3 dB-2000 ms. Further, Q-2000 ms showed approximately a 47 ms delayed latency compared to 3 dB-0 ms. Interestingly, the presence of reverberation significantly increased N400 latencies. Under the distracting conditions, both noise and reverberation involved stronger frontal activation. Conclusions: The current distracting listening conditions could interrupt the semantic mismatch processing in the brain. The presence of reverberation, specifically a 2000 ms delay, necessitates additional mental effort, as evidenced in the delayed N400 latency and the involvement of the frontal sources in this study.

• 한국통신학회논문지
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• 제28권2C호
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• pp.181-192
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• 2003

통신 채널에서 블라인드 등화는 전송효율을 저하시키는 훈련신호나 채널의 사전 정보가 필요치 않은 장점 때문에 많은 연구가 진행되어 왔다. 선형예측을 이용한 블라인드 등화는 등화기의 차수 추정 오차에 강인하며 적응 알고리듬을 이용하여 효율적으로 구현할 수 있는 장점이 있다. 하지만 기존의 one-step 선형예측을 이용한 블라인드 등화기는 임의의 결정 지연에 대해서는 구현할 수 없는 단점이 있다. 본 논문에서는 SIMO 채널에서 one-step 순방향 선형예측 필터를 이용하여 임의의 결정 지연을 갖는 블라인드 등화기를 제안한다. 제안한 알고리듬은 순방향 추정 오차를 훈련신호로 사용하여 최적의 결정 지연을 갖는 블라인드 등화기를 구하였으며 모의실험을 통하여 본 논문에서 제안한 알고리듬의 성능을 확인하였다.

• 융합신호처리학회논문지
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• 제14권2호
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• pp.136-146
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• 2013

본 논문에서는 FX 형식의 한일상관기(Korea-Japan Joint VLBI Correlator, KJJVC)의 잔차 지연 보정 알고리즘을 제안하였다. KJJVC의 초기 잔차 지연보정 알고리즘에는 연산의 고속화를 위해 정수 연산과 위상보정 계수를 위한 cos/sin table을 도입하였다. 그리고 잔차 지연 알고리즘의 초기설계에서 데이터의 타이밍과 잔차 지연 위상의 불일치와 비트쉬프트와 잔차 지연 위상의 불일치 문제를 해결하였다. VCS의 잔차 지연 알고리즘의 최종 설계에서는 잔차 지연보정된 값을 FFT segment에 적용할 때 잔차 지연 보정 회전 메모리가 초기화 되지 않는 것을 수정하였다. 제안한 잔치 지연 보정 알고리즘을 이용하여, 교차 전력 스펙트럼의 대역폭 모양이 모든 대역폭에 대해서 손실이 없이 평탄한 것을 확인하였다. 제안한 잔차 지연보정 알고리즘의 유효성을 확인하기 위해 시뮬레이터와 KJJVC를 이용하여 실제 관측데이터를 대상으로 상관처리 시험을 수행하였다. 실험결과를 통하여 제안한 잔차 지연 보정 알고리즘이 KJJVC에 잘 적용되고 있으며, 신호대 잡음비가 약 8% 향상되는 것을 확인하였다.

• 한국전자파학회논문지
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• 제21권10호
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• pp.1143-1153
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• 2010

본 논문에서는 마이너스 군지연 회로를 이용하여 아날로그 RF 피드백 증폭기의 선형성 개선 대역폭을 증가시킬 수 있는 새로운 방법을 제안한다. 피드백 증폭기는 피드백 경로의 전달 시간 오차로 인하여 선형성 개선 대역폭이 제한되며, 그로 인하여 강력한 선형성 개선 효과에도 불구하고 거의 사용되지 않고 있다. 선행 연구를 통해 설계된 마이너스 군지연 회로의 군지연 특성을 응용하여 기존의 피드백 구조의 한계인 군지연 정합 문제를 해결하였다. 제작된 피드백 증폭기에 2-carrier Wideband Code Division Multiple Access (WCDMA) 신호를 인가하여 측정한 결과, WCDMA 기지국 하향 대역의 50 MHz 대역 전반에 걸쳐서 15 dB 이상의 선형성 개선 효과를 얻을 수 있었다. 평균 출력 전력이 28 dBm일 때 5 MHz 이격된 주파수에서 측정된 인접 채널 누설비(Adjacent Channel Leakage Ratio: ACLR)는 최대 25.1 dB 개선되어 -53.2 dBc로 측정되었다.

• 전력전자학회논문지
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• 제5권2호
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• pp.115-122
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• 2000

3상 PWM 컨버터의 디지털 전류제어기 디자인에 있어서 보편적인 방법은 이산화된 값을 사용한다. 그러나 이같은 시스템은 SVPWM의 특성과 시간연을 고려하지 않았기 때문에 에러를 갖는다. 본 논문은 이와 같은 문제점을 고려한 3상 PWM 컨버터의 새 좌표축 모델을 제시하였으며, 새 모델에 근거한 시지연 보상을 위한 별도의 알고리즘이 필요 없는 직접 디지털 전류제어기를 설계하였다. 또한 제안된 전류제어기를 위한 인덕턴스 불일치 문제를 간단한 알고리즘을 사용하여 보상하였다. 제안된 알고리즘의 타당성을 시뮬레이션과 실험을 통하여 입증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.14-21
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• 2009

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a $0.18{\mu}m$ CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a $0.18{\mu}m$ CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.