• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.1
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• pp.23-33
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• 2002

A hysteresis control is widely used to control output current of inverter. A hysteresis bandwidth is affected by system parameters such as source voltage, device on/off time, load inductance and resistance. The frequency limiter is used to protect switching devices overload. In the conventional hysteresis controller, a lock-out circuit with D-latch and timer is used to device protection circuit. But switching delay time and harmonic components are appeared in output current. In this paper the performance of lock-out circuit is tested, and new circuit for switching device fault protection is proposed ad it's performance is simulated.

• Journal of the Korea Computer Industry Society
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• v.5 no.9
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• pp.841-850
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• 2004

In this paper under the distributed system for efficient distribution resource to system's each node must be designed to get right decision making. Thus we considered computing time to estimate fault such as delay on communication network, communication period and other decision making. Aiso, using direct communitation mode improve the availity of total system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.1-13
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• 1994

In this study under the distributed system for efficient distribution resource completely symmetic global scheduler was designed and implemented to obtain the general global scheduler, that is load balancing as sharing objectives. To balance the system's load efficiently each node must be designed to get right decision-making. Thus we considered computing time to estimate fault such as delay on communication network, communication period and other decision-making. Load balancing mechanism which suggested in this study was implemented in the distributed system which IBM PC/AT linked to and composed with Ethernet. The target operating system was composed of IBM PC/AT as a basic construction in which proper type of UNIX operating system were ported and communication layer chose communication type implemented from Amoeba. The method of IPC employing layered multilevel access method to avoid inefficient protocol using direct communication mode guarantees rapid response due to short ready time for IPC.

• Journal of Electrical Engineering and Technology
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• v.11 no.2
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• pp.353-360
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• 2016

Series hybrid electric vehicles (SHEVs) having multiple power sources such as an engine- generator (EnGen), a battery, and an ultra-capacitor require a power control unit with high power density and reliable control operation. However, manufacturing using separate individual power converters has the disadvantage of low power density and requires a large number of power and signal cable wires. It is also difficult to implement the optimal power distribution and fault management algorithm because of the communication delay between the units. In order to address these concerns, this approach presents a design methodology and a power control algorithm of an integrated power converter for the SHEVs powered by multiple power sources. In this work, the design methodology of the integrated power control unit (IPCU) is firstly elaborately described, and then efficient and reliable power distribution algorithms are proposed. The design works are verified with product-level and vehicle-level performance experiments on a 10-ton SHEV.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.4
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• pp.503-508
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• 2012

Among the high distribution voltage consumers, high-capacity consumers are often applying the grounding resistance method in order to overcome demerits such as erroneous operation of the ground reply or potential increase in the battery at the accident of the isolated neutral system. In this paper, to prevent damage to CLR and GPT in the delay to block the breakdown in the resistance grounded neutral system, this study aims to provide a proper suggestion for continuous rating capacity of GPT to check the appropriateness of CLR size and reduce GPT burden. Thereupon, this study comparatively analyzes CLR current applied in general GPT and the current gained when CLR demanded in the system is used and analyzes the simulated system through simulation using PSCAD/EMTDC in order to suggest GPT's proper continuous rating capacity.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06d
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• pp.369-371
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• 2012

Wireless sensor networks have taken immense interest in healthcare systems in recent years. One example of it is in an in vivo sensor that is deployed in critical and sensitive healthcare applications like artificial retina, cardiac pacemaker, drug delivery, blood pressure, internal heat calculation, glucosemonitoring etc. In vivo sensor nodes exhibit temperature that may be very dangerous for human tissues. However, existing in vivo thermal aware routing approaches suffer from hotspot creation, delay, and computational complexity. These limitations motivate us toward an in vivo virtual backbone, a small subset of nodes, connected to all other nodes and involved in routing of all nodes, -based solution. A virtual backbone is lightweight and its fault-tolerant version allows in vivo sensor nodes to disconnect hotspot paths and to use alternative paths. We have formulated the problem as m-connected k-dominating set problem with minimum temperature cost in in vivo sensor network. This is a combinatorial optimization problem and we have been motivated to use evolutionary approach to solve the problem.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.73-80
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• 1995

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8S
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• pp.2620-2630
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• 2000

본 논문에서는 규칙 기반 추론 기법을 이용하여 LAN 상의 지연 장애 검출 알고리즘과 장애를 유발시킨 호스트에 대한 위치 확인 알고리즘 및 장애 원인 분석 알고리즘을 제시하고자 한다. 이를 위해 지연 장애 검출 모델과 RBR 기반 장애 검출 규칙 모델을 제시하고 있다. 또한 충돌율 검출 규칙과 이용률 검출 규칙을 적용하여 지연 장애 검출 알고리즘을 설계하였고, 최대 패킷 출력 호스트 파악 규칙을 적용하여 장애 위치 탐색 알고리즘을 설계하였다. 그리고 패킷 유형 분석 규칙과 장애 원인 파악 규칙을 적용하여 장애 원인 분석 알고리즘을 설계하였다. 이를 통하여 LAN 상의 지연 장애를 검출하고 진단하는 기법을 제시하고자 한다. 이와 같이 제시한 지연 장애 검출 및 진단 기법을 실제 네트워크 환경에 직접 적용시켜 봄으로써 본 논문에서 제시한 장애 검출 및 진단 기법의 정확성과 적용성을 확인하였다. 이러한 기법은 네트워크 관리자가 LAN 상의 장애를 진단하고 원인을 해결하는데 큰 도움을 줄 것으로 기대된다.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.268-271
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• 2001

This paper presents observer-based on-line overload monitoring scheme for a PMSM(Permanent Magnet Synchronous Motor) drive system. Proposed scheme is to monitor overload status of motor drive system at remote place. The drive system is previously installed on main system and has no communication function. Proposed scheme consists of intelligent sensing head and monitoring part. Intelligent sensing head acquire motor 3-Phase currents and transmit data to monitoring part over serial communication interface. Monitoring part estimates motor speed using state observer. By comparing estimated speed with reference speed, we can detect motor fault. In this scheme observed information must coded and transmitted over a digital communication channel with finite capacity. We consider communication constraint as time delay and we design discrete-time observer. The proposed scheme is tested on the actual drive system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.1
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• pp.22-27
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• 2004

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential behavior. In this paper, proposes a method for efficiently generating test pattern which detect stuck-open in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.