• Title/Summary/Keyword: delay fault

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mproved Spark Streaming Scheduling Mechanism for Real-time Fault Recovery (장애 복구 응답성 향상을 위한 Spark Streaming 스케줄링 개선 메커니즘)

  • Hwang, Yongha;Noh, Soonhyun
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2018.07a
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    • pp.3-6
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    • 2018
  • 최근 방대한 양의 스트림 데이터가 생산되면서 이를 실시간으로 처리하기 위한 프레임워크가 등장하였으며, 오픈 소스 영역에서 Spark Streaming이 주목받고 있다. Spark Streaming은 분산 환경에서 성능 향상을 위해 지연 스케줄링을 기반으로 응용을 수행하지만, 장애 발생 시 사용 가능한 태스크 슬롯을 빠르게 할당받지 못할 경우 장애 복구 시간이 지연될 수 있다는 문제점이 있다. 이러한 문제점을 해결하기 위해 본 논문에서는 실행자의 태스크 슬롯 보장을 통해 대기 시간 없이 즉시 할당할 수 있도록 하는 개선 메커니즘을 제안하였고, 실험 결과 장애 복구 응답성이 39.14% 개선됨을 확인하였다.

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The Dynamic Performance of a Electro-Dynamometer Type Protective Relay for the D.C Component in the Fault Current (전류력계형 계전기의 고장전류중 직류전류분에 의한 동작특성)

  • 이재인
    • 전기의세계
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    • v.27 no.6
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    • pp.54-57
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    • 1978
  • An analytical investigation has been carried out for the motion of moving element in electro-dynamometer type directional power relay under A.C source. For the more a time dependent kinetic performance of the element can also be deduced for the D.C component in fault current. The results obtained thus for show that, in the relay with stopper, the performance time for the equal D.C and A.C component can be shorten ca. 0.5Hz in comparison with the fact, the performance time exhibits to delay ca. 0.75Hz under the same conditions for the case of the relay without stopper, it appear that these differences of performance times will not give vise any difficultys for the apects of practical case, however, the obtain results can be applicable in the course of the design of the relay.

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FTCARP: A Fault-Tolerant Routing Protocol for Cognitive Radio Ad Hoc Networks

  • Che-aron, Zamree;Abdalla, Aisha Hassan;Abdullah, Khaizuran;Rahman, Md. Arafatur
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.8 no.2
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    • pp.371-388
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    • 2014
  • Cognitive Radio (CR) has been recently proposed as a promising technology to remedy the problems of spectrum scarcity and spectrum underutilization by enabling unlicensed users to opportunistically utilize temporally unused licensed spectrums in a cautious manner. In Cognitive Radio Ad Hoc Networks (CRAHNs), data routing is one of the most challenging tasks since the channel availability and node mobility are unpredictable. Moreover, the network performance is severely degraded due to large numbers of path failures. In this paper, we propose the Fault-Tolerant Cognitive Ad-hoc Routing Protocol (FTCARP) to provide fast and efficient route recovery in presence of path failures during data delivery in CRAHNs. The protocol exploits the joint path and spectrum diversity to offer reliable communication and efficient spectrum usage over the networks. In the proposed protocol, a backup path is utilized in case a failure occurs over a primary transmission route. Different cause of a path failure will be handled by different route recovery mechanism. The protocol performance is compared with that of the Dual Diversity Cognitive Ad-hoc Routing Protocol (D2CARP). The simulation results obviously prove that FTCARP outperforms D2CARP in terms of throughput, packet loss, end-to-end delay and jitter in the high path-failure rate CRAHNs.

Design and Evaluation of a Fault-tolerant Publish/Subscribe System for IoT Applications (IoT 응용을 위한 결함 포용 발행/구독 시스템의 설계 및 평가)

  • Bae, Ihn-Han
    • Journal of Korea Multimedia Society
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    • v.24 no.8
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    • pp.1101-1113
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    • 2021
  • The rapid growth of sense-and-respond applications and the emerging cloud computing model present a new challenge: providing publish/subscribe middleware as a scalable and elastic cloud service. The publish/subscribe interaction model is a promising solution for scalable data dissemination over wide-area networks. In addition, there have been some work on the publish/subscribe messaging paradigm that guarantees reliability and availability in the face of node and link failures. These publish/subscribe systems are commonly used in information-centric networks and edge-fog-cloud infrastructures for IoT. The IoT has an edge-fog cloud infrastructure to efficiently process massive amounts of sensing data collected from the surrounding environment. In this paper. we propose a quorum-based hierarchical fault-tolerant publish/subscribe systems (QHFPS) to enable reliable delivery of messages in the presence of link and node failures. The QHFPS efficiently distributes IoT messages to the publish/subscribe brokers in fog overlay layers on the basis of proposing extended stepped grid (xS-grid) quorum for providing tolerance when faced with node failures and network partitions. We evaluate the performance of QHFPS in three aspects: number of transmitted Pub/Sub messages, average subscription delay, and subscritpion delivery rate with an analytical model.

Optimization of Software Cost Model with Warranty and Delivery Delay Costs

  • Lee, Chong-Hyung;Jang, Kyu-Beom;Park, Dong-Ho
    • Communications for Statistical Applications and Methods
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    • v.12 no.3
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    • pp.697-704
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    • 2005
  • Computer software has gradually become an indispensable elements in many aspects of our daily lives and an important factor in numerous systems. In recent years, it is not unusual that the software cost is more than the hardware cost in many situations. In addition to the costs of developing software, the repair cost resulting from the software failures are even more significant. In this paper, a cost model with warranty cost, time to remove each fault detected in the software system, and delivery delay cost is developed. We use a software reliability model based on non-homogeneous Poisson process (NHPP). We discuss the optimal release policies to minimize the expected total software cost. Numerical examples are provided to illustrate the results.

Communication Cable Fault Localization Based on Chirp Signal Parameter Estimation (첩 신호 파라메터 추정 기반 통신 케이블 고장점 탐지에 관한 연구)

  • Lee, Chun-Ku;Han, Seul-Gi;Park, Jin-Bae;Yoon, Tae-Sung
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1782_1783
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    • 2009
  • Reflectometry that has been used to localize faults on a cable is introduced. One of the key point of reflectometry is finding time delay between the incident and reflected signals. In this paper, we propose new reflectometry that use Gaussian enveloped linear chirp signal, and use Kalman filter to estimate frequency rate parameter of the chirp signal. From the estimated frequency rate parameter, we can measure the time delay. In a simulation assuming open ended cable, the proposed method is proved to give a good estimation results.

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Design of Data Retention Test Circuit for Large Capacity DRAMs (대용량 Dynamic RAM의 Data Retention 테스트 회로 설계)

  • 설병수;김대환;유영갑
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.9
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    • pp.59-70
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    • 1993
  • An efficient test method based on march test is presented to cover line leakage failures associated with bit and word lines or mega bit DRAM chips. A modified column march (Y-march) pattern is derived to improve fault coverage against the data retention failure. Time delay concept is introduced to develop a new column march test algorithm detecting various data retention failures. A built-in test circuit based on the column march pattern is designed and verified using logic simulation, confirming correct test operations.

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Fault free Shortest Path routing on the de Bruijin network (드브르젼 네트워크에서 고장 노드를 포함하지 않는 최단 경로 라우팅)

  • Ngoc Nguyen Chi;Nhat Vo Dinh Minh;Zhung Yonil;Lee Sungyoung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.11B
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    • pp.946-955
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    • 2004
  • It is shown that the do Bruijn graph (dBG) can be used as an architecture for interconnection network and a suitable structure for parallel computation. Recent works have classified dBG based routing algorithms into shortest path routing and fault tolerant routing but investigation into fault free shortest path (FFSP) on dBG has been non-existent. In addition, as the size of the network increase, more faults are to be expected and therefore shortest path dBG algorithms in fault free mode may not be suitable routing algorithms for real interconnection networks, which contain several failures. Furthermore, long fault free path may lead to high traffic, high delay time and low throughput. In this paper we investigate routing algorithms in the condition of existing failure, based on the Bidirectional do Bruijn graph (BdBG). Two FFSP routing algorithms are proposed. Then, the performances of the two algorithms are analyzed in terms of mean path lengths and discrete set mean sizes. Our study shows that the proposed algorithms can be one of the candidates for routing in real interconnection networks based on dBG.

A Path Fault Avoided RPAODV Routing in Ad Hoc Networks (Ad Hoc 네트워크의 경로손실 회피기반 RPAODV 라우팅)

  • Wu Mary;Kim Youngrak;Kim Chonggun
    • The KIPS Transactions:PartC
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    • v.11C no.7 s.96
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    • pp.879-888
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    • 2004
  • Ad Node transmits packets to a destination node using routing function of intermediate nodes on the path in Ad Hoc networks. When the link to a next hop node in a path is broken due to the next hop node's mobility, a new route search process is required for continuing packets transmission. The node which recognizes link fault starts a local route recovery or the source node starts a new route search in the on demand routing protocol AODV. In this case, the new route search or the local route search brings packet delays and bad QoSs by packet delay. We propose RPAODV that the node predicts a link fault selects a possible node in neighbor nodes as a new next hop node for the path. The proposed protocol can avoid path faults and improve QoS.

IEEE 1500 Wrapper and Test Control for Low-Cost SoC Test (저비용 SoC 테스트를 위한 IEEE 1500 래퍼 및 테스트 제어)

  • Yi, Hyun-Bean;Kim, Jin-Kyu;Jung, Tae-Jin;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.65-73
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    • 2007
  • This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.