• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.723-726
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• 1998

Fault dropping is a very important part of test generation process. It is used to reduce test generation time. Test generation systems use fault simulation for the purpose of fault dropping by identifying detectable faults with generated test patterns. Two kinds of delay fault model is used in practice, path delay fault model and gate delay fault model. In this paper we propose an efficient method for gate delay test generation which shares second test vector.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.266-276
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• 2001

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has heavily increased. With the increased densities of integrated circuits, several different types of faults can occur Thus, testing such circuits is becoming a sever problem. Delay testing can detect system timing failures caused by delay faults. However, the conventional delay fault coverage in terms of the number of detected faults may not be an effective measure of delay testing because, unlike a stuck-at-faults, the impact of a delay fault is dependent on its delay defect size rather than on its existence. Thus, the effectiveness of delay testing is dependent on the propagation delay of the path to be tested, the delay defect size, and the system clock interval. This paper proposes a new delay defect fault coverage that considers both propagation delay of the path to be tested and additional delay defect size. And the relationship between delay defect fault coverage and defect level is analyzed.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.14-21
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• 1997

In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the delay-optimized design in order to have the same defect-level for delay faults as the non-optimized design, while the system clock time is the same for both designs.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2989-2996
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• 1998

As the circuit density of VLSI grows and its performance improves, delay fault testing of VLSI becomes very important. Delay faults in a circuit can be categorized into two classes, gate delay faults and path delay faults. This paper proposed two methods in dynamic memory usage in the path delay fault simulation. The first method is similar to that used in concurrent fault simulation for stuck-at faults and the second method reduces dynamic memory usage by not inserting a fault descriptor into the fault list when its value is X. The second method, called Implicit-X method, showed superior performance in both dynamic memory usage and simulation time than the first method, called Concurrent-Simulation-Like method.

• Journal of Applied Reliability
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• v.12 no.3
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• pp.215-224
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• 2012

This paper deals with a design of fault tolerant state feedback controllers for continuous time nonlinear time delay systems with actuator failures. The goal is to find an asymptotically stabilizing controller such that the closed loop system achieves the prescribed $H_{\infty}$ performance objective in the actuator fault cases. Based on a sum of squares (SOS) approach, a design method for $H_{\infty}$ fault tolerant controller is presented. In order to demonstrate our design method, a numerical example is provided.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.205-216
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• 1996

In this paper we propose an efficient robust path delay fault test genration algorithm for detection of path delay faluts in combinational ligic circuits. In the proposed robust test genration approach, the testability measure is computed for all gates in the circuit under test and these computed values are used to genrate weighted random delay test vetors for detection of path delay faults. For genrated robust test vectors, we perform fault simulation on ISCAS '85 benchmark circuits using parallel pattern technqieus. The results indicate that the proposed test genration method not only increases the number of detected robust path delay faults but also reduces the time taen to genrate robust tests.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.298-310
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• 1997

Most of the available delay fault simulators for scan environments rely on the use of enhanced scan flip-flops and exclusively consider circuits composed of only discrete gates. In this research, a new path delay fault simulation algorithm using new logic values is devised to enlarge the scope to the VLSI circuits which consist of CMOS elements. Based on the proposed algorithm, a high speed path delay fault simulator for standard scan environments is developed. The experimental results show the new simulator is efficient and accurate.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.12
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• pp.1587-1594
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• 2018

In south korea, the government make a plan to generate the 20% of the total electrical power as renewable source like wind generation and solar generation. This plan will accelerate the increase of fault current with power industry's growth. As the increase of fault current, the superconducting fault current limiter (SFCL) has been studied. In case that the SFCL is applied in power system, it can cause the overcurrent relay (OCR)'s trip delay because of the reduced fault current. In this paper, the overcurrent relay with voltage component was suggested to improve the OCR's trip delay caused by the SFCL and compensational constant was introduced to have the trip time similar to the trip time of case without the SFCL. For conforming the effect of the suggested OCR with voltage component, the PSCAD/EMTDC simulation modeling and analysis were conducted. Through the simulation, it was conformed that the trip delay could be improved by using the suggested OCR and compensational constant.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.1109-1114
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• 1992

Modern chemical processes are becoming more complicated. The sophisticated chemical processes have needed the fault diagnosis pxpert systems that can detect and diagnose the fault diagnosis expert systems that can detect and diagnose the faults of some processes and give and advice to the operator in the event of process faults. We present the Time-Delay Neural Network(TDNN) approach for on-line fautl diagnosis. The on-line fault diagnosis system finds the exact origin of the fault of which the symptom is propagated continuously with time. The proposed method has been applied to a pilot distillation column to show the merits and applicability of the TDNN.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.69-77
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• 2004

An efficient board-level interconnect test algorithm is proposed considering both the ground bounce effect and the delay fault detection. The proposed algorithm is capable of IEEE 1149.1 interconnect test, negative ground bounce effect prevention, and also detects delay faults as well. The number of final test pattern set is not much different with the previous method, even our method enables to detect the delay faults in addition to the abilities the previous method guarantees.