• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.7
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• pp.1390-1406
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• 1994

This study deals with the DMCLP(Delay constrained Minimum Cost Loop Problem)-one of problems arising in the design of local access computer networks. The problem consists of finding a set of rings to satisfy the traffic requirements of end user terminals. In the problem, the objective is to minimize the total link cost. This paper presents heuristic algorithm which consists of two phases for this problem, under the constraints that the number of nodes served by a single ring is limited and network mean delay is dropped within the desired time. The algorithm is derived using the clusters obtained by the existing MCLP(Minimum Cost Loop Problem) algorithm and a trade-off criterion explained in the paper. Actually, simulation results in that the proposed algorithm in this paper produces better solution than the existing MCLP algorithm modified. In addition, the algorithm has the relatively short running time.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.189-192
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• 2000

This paper proposes a fuzzy-based random access controller with a superimposed frame structure (F$^2$RAC) fur voice/data-integrated wireless networks. F$^2$RAC adopts mini-slot technique for reducing contention cost, and these mini-slots of which number may dynamically vary from one frame to the next as a function of the traffic load are further partitioned into two regions for access requests coming from voice and data traffic with their respective QoS requirements. And F$^2$RAC is designed to properly determine the access regions and permission probabilities for enhancing the data packet delay while ensuring the voice packet dropping probability constraint. It mainly consists of the estimator with Pseudo-Bayesian algorithm and fuzzy logic controller with Sugeno-type of fuzzy rules. Simulation results prove that F$^2$RAC can guarantee QoS requirement of voice and provide the highest throughput efficiency and the smallest data packet delay amongst the different alternatives including PRMA［1］, IPRMA［2］, and SIR［3］.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.160-162
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• 2001

Cyclic-Reservation Multiple-Access(CRMA) is an access scheme for high-speed local and metropolitan area networks based on folded-bus or dual-bus configurations. CRMA provides high throughput and fairness independent of the network speed or distance. This paper describes a simulation-based quantitative analysis of the performance gains obtained by introducing slot reuse in CRMA. Generally, a longer cycle length means a longer access delay and a lower throughput. There-fore, it is desirable to develop a scheme such that the cycle length is the shortest. In this paper, we will study the problem of reducing the total number of empty slots generated within every cycle. However, it has been shown that the problem is NP-complete under the constraint that all empty slots used by a station in a cycle are required to be consecutive. We present the algorithm that improves previous novel approach by using previous node information. We compare our slots reuse scheme with several slot reuse algorithms such as region scheme (FMR), address schemes, novel approach in terms of the following two important performance criteria: average cycle length and average slot utilization ratio. As compared with the one proposed in novel algorithm, the new scheme makes the cycle length much shorter. Besides, the resulting slot utilization and the access delay are better than those of the other two schemes.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1322-1333
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• 2014

To track the sinusoidal current under stationary frame and suppress the effects of low-order grid harmonics, the multi-resonant quasi-proportional plus resonant (PR) controller has been extensively used for digitally controlled LCL-type pulse-width modulation (PWM) converters with capacitor-current-feedback active damping. However, designing the controller is difficult because of its high order and large number of parameters. Moreover, the computation and PWM delays of the digitally controlled system significantly affect damping performance. In this study, the delay effect is analyzed by using the Nyquist diagrams and the system stability constraint condition can be obtained based on the Nyquist stability criterion. Moreover, impact analysis of the control parameters on the current loop performance, that is, steady-state error and stability margin, identifies that different control parameters play different decisive roles in current loop performance. Based on the analysis, a simplified controller design method based on the system specifications is proposed. Following the method, two design examples are given, and the experimental results verify the practicability and feasibility of the proposed design method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.3
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• pp.1-10
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• 1997

We present an approach to high-level synthesis for a specific target architecture-partitioned bus architecture. In this approach, we have specific goals of minimizing data transfer length and number of buses in addition to common synthesis goals such as minimizing number of control steps and satisfying given resource constraint. Minimizing data transfer length and number of buses can be very important design goals in the era of deep submicron technology in which interconnection delay and area dominate total delay and area of the chip to be designed. in partitioned bus architecture, to get optimal solution satisfying all the goals, partitioning of operation nodes among segments and ordering of segments as well as scheduling and allocation/binding must be considered concurrently. Those additional goals may impose much more complexity on the existing high-level synthesis problem. To cope with this increased complexity and get reasonable results, we have employed two ideas in ur synthesis approach-extension of the target architecture to alleviate bus requirement for data transfer and adoption of genetic algorithm as a principal methodology for design space exploration. Experimental results show that our approach is a promising high-level synthesis mehtodology for partitioned bus architecture.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1672-1682
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• 2017

For grid-connected LCL-filtered inverters, the inverter-side current can be used as the control object with one current sensor for both LCL resonance damping and over-current protection, while the grid-voltage feedforward or harmonic resonant compensator is used for suppressing low-order grid current harmonics. However, it was found that the grid current harmonics were high and often beyond the standard limitations with this control. The limitations of the inverter-side current control in suppressing low-order grid current harmonics are analyzed through inverter output impedance modeling. No matter which compensator is used, the maximum magnitudes of the inverter output impedance at lower frequencies are closely related to the LCL parameters and are decreased by increasing the control delay. Then, to improve the grid current quality without complicating the control or design, this study proposes designing the filter capacitance considering the current harmonic constraint and using a PWM mode with a short control delay. Test results have confirmed the limitation and verified the performance of the improved approaches.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.6
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• pp.1849-1876
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• 2022

Wireless Sensor Network (WSN) is considered as an integral part of the Internet of Things (IoT) for collecting real-time data from the site having many applications in industry 4.0 and smart cities. The task of nodes is to sense the environment and send the relevant information over the internet. Though this task seems very straightforward but it is vulnerable to certain issues like energy consumption, delay, throughput, etc. To efficiently address these issues, this work develops a cross-layer model for the optimization between MAC and the Network layer of the OSI model for WSN. A high value of duty cycle for nodes is selected to control the delay and further enhances data transmission reliability. A node measurement prediction system based on the Kalman filter has been introduced, which uses the constraint based on covariance value to decide the scheduling scheme of the nodes. The concept of duty cycle for node scheduling is employed with a greedy data forwarding scheme. The proposed Duty Cycle-based Greedy Routing (DCGR) scheme aims to minimize the hop count, thereby mitigating the energy consumption rate. The proposed algorithm is tested using a real-world wastewater treatment dataset. The proposed method marks an 87.5% increase in the energy efficiency and reduction in the network latency by 61% when validated with other similar pre-existing schemes.

• The KIPS Transactions:PartC
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• v.9C no.4
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• pp.543-550
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• 2002

This paper proposes the dynamic slot allocation method for real-time VBR (rt-VBR) services in wireless ATM networks. The proposed method is characterized by a contention-based mechanism of the reservation request, a contention-free polling scheme for transferring the dynamic parameters. The base station scheduler allocates a dynamic parameter minislot to the wireless terminal for transferring the residual lifetime and the number of requesting slots as the dynamic parameters. The scheduling algorithm uses a priority scheme based on the maximum cell transfer delay parameter. Based on the received dynamic parameters, the scheduler allocates the uplink slots to the wireless terminal with the most stringent delay requirement. The simulation results show that the proposed method guarantee the delay constraint of rt-VBR services along with its cell loss rate significantly reduced.

• Journal of Korean Society of Transportation
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• v.27 no.6
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• pp.147-156
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• 2009

We present a methodology for modeling and solving the transit frequency design problem with variable demand. The problem is described as a bi-level model based on a non-cooperative Stackelberg game. The upper-level operator problem is formulated as a non-linear optimization model to minimize net cost, which includes operating cost, travel cost and revenue, with fleet size and frequency constraints. The lower-level user problem is formulated as a capacity-constrained stochastic user equilibrium assignment model with variable demand, considering transfer delay between transit lines. An efficient algorithm is also presented for solving the proposed model. The upper-level model is solved by a gradient projection method, and the lower-level model is solved by an existing iterative balancing method. An application of the proposed model and algorithm is presented using a small test network. The results of this application show that the proposed algorithm converges well to an optimal point. The methodology of this study is expected to contribute to form a theoretical basis for diagnosing the problems of current transit systems and for improving its operational efficiency to increase the demand as well as the level of service.

• Journal of Advanced Navigation Technology
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• v.22 no.6
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• pp.557-565
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• 2018

For GNSS navigation in urban environment, a novel short delay multipath mitigation algorithm is proposed in this paper. This algorithm detects which satellite's signal is the multipath signal by using the constraint that GNSS receiver is equipped in a ground vehicle, then estimate new position after separating the measurement of that satellite. A criterion for detecting and validating the multipath signal depends on the performance grade of the GNSS receiver and the dynamics of the vehicle. In order to evaluate the proposed algorithm, the real data had been collected at the multipath environment of 4 scenarios. By post-processing the real data with both of the multipath mitigation algorithm in the receiver and the proposed algorithm, it can be checked that the position errors were less than 5 meters except the case that the number of visible satellite is lower than 5.