• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.468-472
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• 2004

In this paper a VLSI design for the automatic magnetizing system has been presented. This is the design of a peripheral controller, which magnetizes CRTs and computers monitors and controls the automatic inspection system. We implemented a programmable peripheral interface(PPI) circuit of the control and protocol module for the magnetizer controller by using a O.8um CMOS SOG(Sea of Gate) technology of ETRI. Most of the PPI functions has been confirmed. In the conventional method, the propagation/ramp delay model was used to predict the delay of cells, but used to model on only a single cell. Later, a modified "apos;Linear delay predict model"apos; was suggested in the LODECAP(LOgic Design Capture) by adding some factors to the prior model. But this has not a full model on the delay chain. In this paper a new "apos;delay predict equationapos;" for the design of the timing control block in PPI system has been suggested. We have described the detail method on a design of delay chain block according to the extracted equation and applied this method to the timing control block design.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.95-98
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• 1998

In this paper, we propose a cell scheduling algorithm for ABR traffic in ATM multiplexer. Proposed Algorithm can support ABR service more efficiently than existing WRR and DWRR algorithm. We evaluate the performances of proposed algorithm through computer simulation. Also, we model the VBR and the ABR traffics as ON/OFF source, and the CBR traffic as a Poisson source. And the simulation shows that proposed algorithm better performance over other cell scheduling algorithm in tem of mean cell delay time.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.85-88
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• 2002

Maintaining a proper level of cell lead, system throughput can be maximized by a transmission rate control over the uplink in DS/CDMA cellular system to support integrated services of real-time and delay-tolerant traffic. We find that the cell load-based rate control scheme can be further enhanced by taking the varying channel condition into account In conjunction with some fair scheduling algorithm. Our simulation results show that the proposed scheme outperforms the original cell load-based rate control with the round-robin sharing scheduling scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.604-612
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• 2000

In order to satisfy the desired QoS level associated with each existing connection, ATM networks require traffic policing during a connection. Users who respect the contract should receive the function of transparent traffic policing without any interruption. However, contract violations should be detected and mediated immediately. So we propose a CAM type policing controller to allow user cell streams to minimize additional delay. The proposed policing scheme controls policing actions including traffic shaping by suitably spacing cells on each virtual circuit. This policing action is based on parallel processing of multiple cell stream which arrive in ATM multiplexed virtual circuits. We have developed an analytical model of the proposed policing scheme to examine the amount of cell loss and delay, which depends on traffic load, the size of policing buffers and minimum spacing cell time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.1891-1901
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• 2017

In this paper, optimal control of the fuel cell and design of a high-efficiency power converter is implemented to build a high-priced fuel cell system with minimum capacity. Conventional power converter devices use a non-isolated boost converter for high efficiency while the battery is charged, and reduce its conduction loss by using MOSFETs instead of diodes. However, the efficiency of the boost converter decreases, since overshoot occurs because there is a moment when the body diode of the MOSFET is conducted during the dead time and huge loss occurs when the dead time for the maximum-power-flowing state is used in the low-power-flowing state. The method proposed in this paper is to adjust the dead time of boost and rectifier switches by predicting the power flow to meet the maximum efficiency in every load condition. After analyzing parasite components, the stability and efficiency of the high-efficiency boost converter is improved by predictive compensation of the delay component of each part, and it is proven by simulation and experience. The variation in switching delay times of each switch of the full-bridge converter is compensated by falling time compensation, a control method of PWM, and it is also proven by simulation and experience.

• Journal of Korea Multimedia Society
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• v.4 no.4
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• pp.339-348
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• 2001

In this paper, a cell scheduling algorithm which can be applied to all of the service class in ATM network is proposed. The proposed algorithm classifies the order of priority in each service class into 4 categories and generates the weight of each class service based on the traffic parameters which are negotiated in connection contract. The proposed algorithm guarantees QoS(Quality of Service) to the traffic which is sensitive to delay carrying out CBR and rt_VBR service. As it effectively manages the connection which has small bandwidth, it minimizes the cell delay in the queue. For verifying the effectiveness of the proposed algorithm the proposed algorithm is simulated with existing cell scheduling algorithm and the result is showed.

• Journal of Communications and Networks
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• v.6 no.3
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• pp.216-225
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• 2004

In a cellular network, if there are too many data users in a cell, data may suffer long delay, and system's quality-of-service (QoS) will degrade. Some traditional schemes such as dynamic channel-allocation scheme (DCA) will assign more channels to hot (or overloaded) cells through a central control system (CC) and the throughput increase will be upper bounded by the number of new channels assigned to the cell. In mobile-assisted data forwarding (MADF), we add an ad-hoc overlay to the fixed cellular infrastructure and special channels-called forwarding channels- are used to connect mobile units in a hot cell and its surrounding cold cells without going through the hot cell's base station. Thus, mobile units in a hot cell can forward data to other cold cells to achieve load balancing. Most of the forwarding-channel management work in MADF is done by mobile units themselves in order to relieve the load from the CC. The traffic increase in a certain cell will not be upper bounded by the number of forwarding channels. It can be more if the users in hot cell are significantly far away from one another and these users can use the same forwarding channels to forward data to different cold neighboring cells without interference. We find that, in a system using MADF, under a certain delay requirement, the throughput in a certain cell or for the whole net-work can be greatly improved.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.119-125
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• 2000

A network of Asynchronous Transfer Mode (ATM) will be required to carry the traffics(CVR, VBR, UBR, ABR) generated by a wide range of services. The algorithm of WRR cell multiplexing is designed to serve no only CBR, VBR traffic but also ABR, UBR traffic in ATM. BSW algorithm was Proposed to carry on manage buffer efficiently at implementing of WRR scheduler. But, BSW a1gorithm cause serious degradation to the weight of each VC and the ratio of scheduler throughput because it allocates more weight than the weight allocated actually in VC and because it could not serve cell if the VC queue is empty. In this paper, we propose the WRR scheduling algorithm of BSW structure which improves the cell service ratio and cell delay. The proposed algorithm is capable of maintaining an allocated VC's weight correctly and decrease of average cell delay by serving other VC cell when empty in each VC queue and increase of cell service ratio as a whole.