• Title/Summary/Keyword: decoding delay

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Performance of Iterative Equalizer for ISI channel

  • Nguyen, Quoc Kien;Jeon, Taehyun
    • International journal of advanced smart convergence
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    • v.9 no.3
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    • pp.141-144
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    • 2020
  • Iterative decision feedback equalizer (IDFE) is a recursive equalization technique that can help to achieve an additional performance gain for the system by combining iterative channel decoding and interference cancellation. In a single carrier-based system, the intersymbol interference (ISI) is a critical problem that must be resolved since it causes frequency selective fading. Based on the idea of sharing the estimated information in the process of iteration, IDFE is considered as an efficient solution to improve the robustness of the system performance on the ISI channel. In this paper, the IDFE is applied on single carrier FDMA (SC-FDMA) system to evaluate the performance under ISI channel. The simulation results illustrate that IDFE helps to improve the performance of the SC-FDMA system, especially with long delay spread channels.

Pipelined Successive Interference Cancellation Schemes with Soft/Hard Tentative Decision Functions for DS/CDMA Systems (DS/CDMA 시스템에서 연/경판정 함수를 적용한 파이프라인화된 직렬 간섭 제어 기법)

  • 홍대기;백이현;김성연;원세호;강창언
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.11A
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    • pp.1652-1660
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    • 2000
  • 본 논문에서는 DS/CDMA (Direct Sequence/Code Division Multipe Access) 시스템에서 임시 판정 함수로서 연판정 함수와 경판정 함수를 적용한 파이프라인화된 직렬 간섭 제어 구조(PSIC, Pipelined Successive Interference Cancellation)의 성능을 수식적으로 분석하고, 모의 실험을 통하여 검증한다. PSIC 구조는 다단 직렬 간섭 제거 구조(MSIC, Multistage Successive Interference Cancellation)가 가지는 복호지연(decoding delay)의 문제를 해결하기 위해 파이프라인 구조를 MSIC에 적용한 것이다. 제안된PSIC 구조는 하드웨어의 복잡도(hardwar complexity)를 희생하여 비트 오율(BER, Bit Error Rate)의 증가 없이 MSIC에서 발생하는 복호 지연을 줄일 수 있다. 또한 제안된 PSIC 구조에서 연판정 함수와 경판정 함수를 각 간섭 제거 단(Cancellation stage)에서의 임시 판정 함수로 사용하여 얻게 되는 PSIC 구조들의 성능을 비교한다. 분석 및 실험 결과에 의하면 제안되 PSIC 구조에서는 경판정 함수를 사용할때의 성능이 연판정 함수를 사용할때의 성능보다 우수함을 알 수 있었다.

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A VLSI Architecture for Novel Decision Feedback Differential Phase Detection with an Accumulator

  • Kim, Chang-Kon;Chong, Jong-Wha
    • ETRI Journal
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    • v.24 no.2
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    • pp.161-171
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    • 2002
  • This paper proposes a novel decision feedback differential phase detection (DF-DPD) for M-ary DPSK. A conventional differential phase detection method for M-ary Differential Phase Shift Keying (DPSK) can simplify the receiver architecture. However, it possesses a poorer bit error rate (BER) performance than coherent detection because of the prior noisy phase sample. Multiple-symbol differential detection methods, such as maximum likelihood differential phase detection, Viterbi-DPD, and DF-DPD using L-1 previous detected symbols, have attempted to improve BER performance. As the detection length, L, increases, the BER performance of the DF-DPD improves but the complexity of the architecture increases dramatically. This paper proposes a simplified DF-DPD architecture replacing the conventional delay and additional architecture with an accumulator. The proposed architecture also improves BER performance by minimizing the current differential phase noise through the accumulation of previous differential phase noise samples. The simulation results show that the BER performance of the proposed architecture approaches that of a coherent detection with differential decoding.

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Comparative Performance Analysis of Network Security Accelerator based on Queuing System

  • Yun Yeonsang;Lee Seonyoung;Han Seonkyoung;Kim Youngdae;You Younggap
    • Proceedings of the IEEK Conference
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    • summer
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    • pp.269-273
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    • 2004
  • This paper presents a comparative performance analysis of a network accelerator model based on M/M/l queuing system. It assumes the Poisson distribution as its input traffic load. The decoding delay is employed as a performance analysis measure. Simulation results based on the proposed model show only $15\%$ differences with respect to actual measurements on field traffic for BCM5820 accelerator device. The performance analysis model provides with reasonable hardware structure of network servers, and can be used to span design spaces statistically.

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A Design of Turbo Decoder for 3GPP using Log-MAP Algorithm (Log-MAP을 사용한 3GPP용 터보 복호기의 설계)

  • Kang, Heyng-Goo;Jeon, Heung-Woo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.1
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    • pp.533-536
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    • 2005
  • MAP algorithm is known for optimal decoding algorithm of Turbo codes, but it has very large computational complexity and delay. Generally log-MAP algorithm is used in order to overcome the defect. In this paper we propose modified scheme of the state metric calculation block which can improve the computation speed in log-MAP decoder and simple linear offset unit without using LUT. The simulation results show that the operation speed of the proposed scheme is improved as compared with that of the past scheme.

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The Improved Success Rate of Integer Ambiguity Resolution by Using Many Visible GPS/GNSS Satellites

  • Kondo, Kentaro
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.2
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    • pp.243-246
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    • 2006
  • This study investigates the improvement in the theoretical success rate of the integer ambiguity resolution in GPS/GNSS carrier-phase positioning by using many visible satellites. It estimates the dependence of the rate on the baseline length in relative positioning under the condition of the use of double/triple-frequency navigation signals. The calculation results show that the use of 14 navigation satellites (i.e., seven GPS and seven Galileo ones) remarkably improves the success rate under the condition of very short baseline length, compared with the use of seven GPS ones. The numerical reliability of the calculated success rates is strictly tested by examining the tightness of the union and minimum-distance bounds to the rate. These bounds are also shown to be effective to investigate the realization of the high success rates.

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Performance Improvement of MIMO-OFDMA system with beamformer

  • Kim, Chan Kyu
    • International Journal of Internet, Broadcasting and Communication
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    • v.11 no.1
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    • pp.60-68
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    • 2019
  • In this paper, we propose the adaptive beamforming algorithm for the MIMO (Multi-Input Multi-Out)-OFDMA(Orthogonal Frequency Division Multiplexing Access)system to improve the performance. The performance of MIMO-OFDMA systems is greatly decreased in the wireless channel environment with multiusers, because the received signals are much distorted by a cochannel interference (CCI) during the space-time decoding. The proposed approach can track the DOA of each signal from the multiple antennas of the desired user without being greatly dependent on the impinging angle. And beams are directed toward the multiple transmitters of the desired user while null beams are directed toward interference directions. Therefore, we can can effectively cancel CCI and mitigate the impairment of delay spread while preserving the STC(space time code) diversity. BER performance improvement is investigated through computer simulation by applying the proposed approach to MIMO-OFDMA system in a multipath fading channel with CCI.

A Study on High Speed LDPC Decoder Algorithm based on dc saperation (dc 분리 기반의 고속 LDPC 복호 알고리즘에 관한 연구)

  • Kwon, Hae-Chan;Kim, Tae-Hoon;Jung, Ji-Won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.9
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    • pp.2041-2047
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    • 2013
  • In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed dc-split memory structure in order to reduced the delay and high speed decoder is possible. Finally, this paper presented maximum split memory and throughput for various coding rates in DVB-S2 standard.

Performance of Turbo Coded OFDM Systems in W-CDMA Wireless Communication Channel (W-CDMA 무선통신 채널에서 터보 부호를 적용한 OFDM 시스템의 성능 분석)

  • Shin, Myung-Sik;Yang, Hae-Sool
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.10 no.4
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    • pp.183-191
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    • 2010
  • In the recent digital communication systems, the performance of Turbo Code used as the error correction coding method depends on the interleaver size influencing the free distance determination and the iterative decoding algorithms of the turbo decoder. However, some iterations are needed to get a better performance, but these processes require a large time delay. Recently methods of reducing the number of iteration have been studied without degrading original performance. In this paper, the new method of combining ME (Mean Estimate) stopping criterion with SDR (sign difference ratio) stopping criterion among previous stopping criteria is proposed, and the fact of compensating each method's missed detection is verified. Faster decoding is realized that about 1~2 time iterations to reduced through adopting this method into serially concatenated both decoders. System Environments were assumed W-CDMA forward link system with intense MAI (multiple access interference).

Hardware design of Reed-solomon decoder for DMB mobile terminals (DMB 휴대용 단말기를 위한 Reed-Solomon 복호기의 설계)

  • Ryu Tae-Gyu;Jeong Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.4 s.346
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    • pp.38-48
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    • 2006
  • In this paper, we developed a hardware architecture of Reed-Solomon RS(255,239) decoder for the DMB mobile terminals. The DMB provides multimedia broadcasting service to mobile terminals, hence it should have small dimension for low power and short decoding delay for real-time processing. We modified Euclid algorithm to apply it to the key equation solving which is the most complicated part of the RS decoding. We also designed a small finite field divider to avoid the use of large Inverse-ROM table, and it consumed 17 clocks. After synthesis with Synopsis on Samsung STD130 $0.18{\mu}m$ Standard Cell library, the Euclid block had 30,228 gates and consumed 288 clocks, which gave the 25% reduced area compared to other existing designs. The size of the entire RS decoder was about 45,000 gates.