• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2007년도 하계종합학술대회 논문집
• /
• pp.177-178
• /
• 2007

WiBro system provides reliable broadband communication services for mobile and portable subcribers. It allows interference-free reception under the conditions of multipath propagation and transmission errors. Thus, powerful channel-error correction ability Is required. CC/CTC Decoder which Is mandatory for WiBro system needs lots of computations for real-time operation. So, it is desired to design a CC/CTC Decoder having highly optimized hardware scheme for low latency operation under high data rates. This paper proposes an efficient CC/CTC Decoder structure for high data rate WiBro system. Particularly, the proposed CTC Decoder architecture reduces decoding delay by applying pipelining and multiple decoding blocks. Simulation results show that reduction of about 80% of processing time is enabled with the proposed CC/CTC Decoder despite of increase in are.

• 전기학회논문지
• /
• 제58권5호
• /
• pp.1035-1040
• /
• 2009

We propose a new encoder/decoders based on an tune able wavelength converter(TWC) and an arrayed waveguide grating(AWG) router for large capacity optical CDMA networks. The proposed encoder/decoder treats codewords of wavelength/time 2-D code simultaneously using the dynamic code allocation property of the TWC and the cyclic property of the AWG router, and multiple subscribers can share the encoder/decoder in networks. Feasibility of the structure of the proposed encoder/decoder for dynamic code allocation is tested through simulations using two wavelength/time 2-D codes, which are the generalized multi-wavelength prime code(GMWPC) and the generalized multi-wavelength Reed-Solomon code(GMWRSC). Test results show that the proposed encoder/decoder can increase the channel efficiency not only by increasing the number of simultaneous users without any multiple-access interference but by using a relatively short length CDMA codes.

• 정보저장시스템학회논문집
• /
• 제1권2호
• /
• pp.155-160
• /
• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• 대한임베디드공학회논문지
• /
• 제4권4호
• /
• pp.195-200
• /
• 2009

As 4G mobile communication systems require high transmission rates with reliability, the need for efficient error correcting code is increasing. In this paper, a novel LDPC (Low Density Parity Check) decoder is introduced. The LDPC code is one of the most popular error correcting codes. In order to improve performance of the LDPC decoder, we use SNR (Signal-to-Noise Ratio) estimation results to adjust coefficients of modified UMP-BP (Uniformly Most Probable Belief Propagation) algorithm which is one of widely-used LDPC decoding algorithms. An advantage of Modified UMP-BP is that it is amenable to implement in hardware. We generate the optimal values by simulation for various SNRs and coefficients, and the values are stored in a look-up table. The proposed decoder decides coefficients of the modified UMP-BP based on SNR information. The simulation results show that the BER (Bit Error Rate) performance of the proposed LDPC decoder is better than an LDPC decoder using a conventional modified UMP-BP.

• 한국통신학회논문지
• /
• 제39A권4호
• /
• pp.180-187
• /
• 2014

본 논문에서는, 하향 다중 사용자 MIMO 환경에서 간섭 검출 및 제거를 하기위해 확장된 fixed-complexity sphere decoder (FSD) 알고리즘이 제안되었다. 제안된 알고리즘은, generalized sphere decoder (GSD) 알고리즘을 이용한 채널행렬 확장과 간섭신호와 요구신호를 고려한 채널행렬 순서화를 통해 FSD 알고리즘을 간섭신호 검출에 활용 가능하도록 확장 하였다. IEEE802.11ac의 통신모드 중 네 명의 다중 사용자에게 각각 702 Mbit/s 전송이 가능한 환경의 몬테카를로실험을 통해서, 제안된 알고리즘이 10% packet error rate기준으로 간섭제거 기능이 없는 maximum-likelihood 검출성능 대비 $E_b/N_0$가 약 3 dB 향상됨을 보여주었다.

• 디지털산업정보학회논문지
• /
• 제15권4호
• /
• pp.85-92
• /
• 2019

This paper presents a SDR-based Long Term Evolution Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a multicore Digital Signal Processor (DSP). For decoder implementation, multicore DSP TMS320C6670 is used, which provides various hardware accelerators such as turbo decoder, fast Fourier transformer and Bit Rate Coprocessors. The TMS320C6670 is a DSP specialized in implementing base station platforms and is not an optimized platform for implementing mobile terminal platform. Accordingly, in this paper, the hardware accelerator was changed to the terminal implementation to implement the LTE-A PDSCH decoder supporting the multi-antenna and the functions not provided by the hardware accelerator were implemented through core programming. Also pipeline using multicore was implemented to meet the transmission time interval. To confirm the feasibility of the proposed implementation, we verified the real-time decoding capability of the PDSCH decoder implemented using the LTE-A Reference Measurement Channel (RMC) waveform about transmission mode 2 and 3.

• 한국통신학회논문지
• /
• 제36권4C호
• /
• pp.191-196
• /
• 2011

본 논문에서는 오류정정 능력이 비교적 작은 경우에 매우 효율적인 직접복호법을 이용하여 기존의 복호기에 비해 하드웨어적으로 매우 간단한 UWB 용 (23, 17) Reed-Solomon 복호기의 설계 방법을 제안한다. 설계된 복호기는 오류위치다항식 및 오류평가다항식의 계산에 $GF(2^m)$ 상의 곱셈기가 9개만 사용되어, 기존의 복호기가 약 20여개가 소요되는데 비해 매우 간단한 하드웨어로 구현할 수 있는 장점을 가지고 있다. 또한 제어회로도 매우 간단하고, 복호지연도 오증계산에 걸리는 한 블록만큼만 소요되므로 수신 시퀀스를 저장하는 버퍼 메모리를 절약할 수 있다.

• 한국가시화정보학회지
• /
• 제22권1호
• /
• pp.49-60
• /
• 2024

The purpose of this study establishes the deep neural network (DNN) and Decoder models to predict the flow and thermal fields of three-dimensional wavy wings as a passive flow control. The wide ranges of the wavy geometric parameters of wave amplitude and wave number are considered for the various the angles of attack and the aspect ratios of a wing. The huge dataset for training and test of the deep learning models are generated using computational fluid dynamics (CFD). The DNN and Decoder models exhibit quantitatively accurate predictions for aerodynamic coefficients and Nusselt numbers, also qualitative pressure, limiting streamlines, and Nusselt number distributions on the surface. Particularly, Decoder model regenerates the important flow features of tiny vortices in the valleys, which makes a delay of the stall. Also, the spiral vortical formation is realized by the Decoder model, which enhances the lift.

• ETRI Journal
• /
• 제46권3호
• /
• pp.485-500
• /
• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• 전자공학회논문지
• /
• 제50권11호
• /
• pp.50-57
• /
• 2013

본 논문은 하나 이상의 다양한 길이의 패킷을 동시에 복호할 수 있는 고 처리율 병렬 터보 복호기의 설계를 보인다. 터보 복호기의 병렬 구조는 반복 복호로 인한 긴 디코딩 시간을 절감시키며, 입/출력의 이중 버퍼 구조 설계는 패킷들의 연속적인 복호를 가능하게 함으로써 복호기의 처리율을 향상시킨다. 병렬 터보 복호기는 가장 긴 길이의 패킷을 복호할 수 있도록 설계되기 때문에, 이보다 짧은 길이의 패킷의 복호 시에는 사용하지 않는 PE(Processing Element)가 존재한다. 본 논문의 아이디어는 이 유휴 PE들을 연속적으로 이어지는 다음 패킷의 복호에 즉시 이용함으로써, 복호기 내의 PE 사용 효율을 높이고 처리율을 향상시키는 데 있다. 이를 위하여 여러 패킷의 복호를 동시에 가능하게 하는 제어가 필요하며, 본 논문에서는 이러한 제어 방법을 기술한다. 제안한 방법을 적용하여, 32개의 PE를 사용하면서 최대 6144비트 길이의 패킷을 복호 할 수 있는 병렬 터보 복호기를 구현하였으며, 기존 터보 복호기와 비교하여 약 16% 의 면적 증가가 있었으나, 짧은 패킷의 경우 기존 복호기에 비해 최대 28배의 높은 처리율 향상 효과를 보였다.