• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.19-26
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• 2005

After various video coding standards such as H.263, MPEG-4, and H.264 have been introduced, there has bun strong need to support the multiple standards with limited resources efficiently. In terms of deblocking Inter which plays an important role in improving visual quality, K264 deblocking filter implementation has different aspects as compared with traditional $8\times8$ block-based post-filter implementation. Analyzing the differences, this paper proposes a H.264 deblocking filter implementation method that supports $8\times8$ block-based post-filtering for the traditional video coding systems. In the proposed implementation method the block boundaries to he filtered are adaptively chosen for $8\times8$ and $4\times4$ block boundary filtering. Since the filtered result is selectively used for motion compensation or not, both loop-filtering and post-filtering can be achieved. A quantization parameter conversion unit that converts H.263 quantization parameters to H.264 quantization parameters is utilized by examining the $8\times8$ block boundary errors based on human visual system. Since the original nature of the H.264 deblocking filter is well expanded to the $8\times8$ block-based post-filter with minor modifications, the proposed implementation method is suitable to implement the deblocking function of the multiple video standards such as H.263, MPEG-4, and K264, efficiently.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.755-758
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• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.

• Journal of Information Processing Systems
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• v.12 no.4
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• pp.631-643
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• 2016

Due to the block-based discrete cosine transform (BDCT), JPEG compressed images usually exhibit blocking artifacts. When the bit rates are very low, blocking artifacts will seriously affect the image's visual quality. A bilateral filter has the features for edge-preserving when it smooths images, so we propose an adaptive-weighted bilateral filter based on the features. In this paper, an image-deblocking scheme using this kind of adaptive-weighted bilateral filter is proposed to remove and reduce blocking artifacts. Two parameters of the proposed adaptive-weighted bilateral filter are adaptive-weighted so that it can avoid over-blurring unsmooth regions while eliminating blocking artifacts in smooth regions. This is achieved in two aspects: by using local entropy to control the level of filtering of each single pixel point within the image, and by using an improved blind image quality assessment (BIQA) to control the strength of filtering different images whose blocking artifacts are different. It is proved by our experimental results that our proposed image-deblocking scheme provides good performance on eliminating blocking artifacts and can avoid the over-blurring of unsmooth regions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.63-72
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• 2012

In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.142-148
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• 2008

Though a deblocking filter of H.264/AVC provides enhanced image quality by removing blocking artifact on block boundary, the complex filtering operation on this process is a dominant factor of the whole decoding time. In this paper, we designed an ASIP to accelerate deblocking filter operation with the proposed instruction set. We designed a processor based on a MIPS structure with LISA, simulated a deblocking later model, and compared the execution time on the proposed instruction set. In addition, we generated HDL model of the processor through CoWare's Processor Designer and synthesized with TSMC 0.25um CMOS cell library by Synopsys Design Compiler. As the result of the synthesis, the area and delay time increased 7.5% and 3.2%, respectively. However, due to the proposed instruction set, total execution performance is improved by 18.18% on average.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.6
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• pp.30-35
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• 2007

H.264/AVC provides better quality than other algorithms by using a deblocking filter to remove blocking distortion on block boundary of the decoded picture. However, this filtering process includes lots of memory accesses, which cause delay of overall decoding time. In this paper, we propose a data-reuse algorithm to speed up the process for the deblocking filter. To reuse the data, a new filtering order is suggested. By using this order, we reduce the memory access and accelerate the deblocking filter. The modeling of proposed algorithm is compiled under ARM ADS1.2 and simulated with Armulator. The results of the experiment compared with H.264/AVC standard are achieved on average 58.45% and 57.93% performance improvements at execution cycles and memory access cycles, respectively.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.735-738
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• 2005

This paper presents an AMBA-based IP that can perform the deblocking filtering operations required in the H.264 video compression. The deblocking filter circuit was optimized for area and performance. The AHB wrapper was added to the circuit to interface with the AMBA-based platform. The AMBA-compliant operation of the proposed IP was verified on the platform board with Xilinx Virtex2 XC2V600 FPGA and ARM9 processor.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.46-49
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• 2000

An iterative deblocking algorithm for DCT-compressed images using two-dimensional FIR filters adapted for local directionality of each block, is proposed. First, we introduce a set of simple lowpass filters, which are adapted for edges of different angles. In conventional deblocking methods based on lowpass-filtering and convex projections, a single filter is applied to a whole image. In the proposed method, on the other hand, a suitable filter is chosen out of the directional filters designed previously in every subimage (typically $8{\times}8$ block). Experimental results indicate that adaptive filtering improves PSNR at each iteration.

• ETRI Journal
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• v.32 no.2
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• pp.336-338
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• 2010

A macroblock-level deblocking method is proposed for H.264/AVC, in which blocking artifacts are effectively eliminated in the discrete cosine transform domain at the macroblock encoding stage. Experimental results show that the proposed algorithm outperforms conventional H.264 in terms of coding efficiency, and the bitrate saving is up to 5.7% without reconstruction quality loss.