• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.21-23
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• 1998

본 논문에서 ILP (Instruction Level Parallelism)의 성능향상을 위하여 데이터 값들을 미리 예측하여 병렬로 이슈(issue)하고 수행하는 기존의 데이터 값 예측기(data value predictor)를 비교 분석하여 각 예측기의 예측율을 측정하고, 2-단계 데이터 값 예측기(Two-Level Data Value Predictor)와 혼합형 데이터 값 예측기(Hydrid Data Value Predictor)에서 발생되는 aiasing 을 측정하기 위해 수정된 데이터 값 예측기를 사용하여 측정한 결과 aliasing은 50% 감소하였지만 예측율에는 영향을 미치지 못함과 데이터 값 예측기의 예측율을 측정한 결과 혼합형 데이터 값 예측기의 예측율이 2-단계 데이터 값 예측기와 스트라이드 데이터 값 예측기(Stride Data Value Predictor)에서 평균 5.7%, 최근 값 예측기(Last Data Value Predictor)보다는 평균 38%의 예측 정확도가 높음을 입증하였다.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.235-238
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• 2003

Conventional stride predictor is useful for predicting data values which vary by a constant value. However, when the data values of shift, multiplication, and division instructions are predicted, the stride predictor can't show the best performance. Thus, we propose predictor using stride and shift to improve predictability. The predictor using stride and shift takes advantage of shift values as well as stride values, so that the overall coverage of prediction increases.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.107-115
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• 2002

We propose a new hybrid value predictor which achieves high performance by combining several predictors. Because the proposed hybrid value predictor can update the prediction table speculatively, it efficiently reduces the number of mispredicted instructions due to stale data. Also, the proposed predictor can enhance the prediction accuracy and efficiently decrease the hardware cost of predictor, because it allocates instructions into the best-suited predictor during instruction fetch stage by using the information of static classification which is obtained from the profile-based compiler implementation. For the 16-issue superscalar processors, simulation results based on the SimpleScalar/PISA tool set show that we achieve the average prediction rates of 73% by using speculative update and the average prediction rates of 88% by adding static classification for the SPECint95 benchmark programs.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.741-751
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• 2000

To achieve high performance by exploiting instruction level parallelism aggressively in superscalar processors, it is necessary to overcome the limitation imposed by control dependences and data dependences which prevent instructions from executing parallel. Value prediction is a technique that breaks data dependences by predicting the outcome of an instruction and executes speculatively its data dependent instruction based on the predicted outcome. In this paper, a hybrid value prediction scheme with dynamic classification mechanism is proposed. We design a hybrid predictor by combining the last predictor, a stride predictor and a two-level predictor. The choice of a predictor for each instruction is determined by a dynamic classification mechanism. This makes each predictor utilized more efficiently than the hybrid predictor without dynamic classification mechanism. To show performance improvements of our scheme, we simulate the SPECint95 benchmark set by using execution-driven simulator. The results show that our scheme effect reduce of 45% hardware cost and 16% prediction accuracy improvements comparing with the conventional hybrid prediction scheme and two-level value prediction scheme.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.601-612
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• 2001

In superscalar processors, value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction in order to exploit instruction level parallelism(ILP). A value predictor looks up the prediction table for the prediction value of an instruction in the instruction fetch stage, and updates with the prediction result and the resolved value after the execution of the instruction for the next prediction. However, as the instruction fetch and issue rates are increased, the same instruction is likely to fetch again before is has been updated in the predictor. Hence, the predictor looks up the stale value in the table and this mostly will cause incorrect value predictions. In this paper, a stride value predictor with the capability of speculative updates, which can update the prediction table speculatively without waiting until the instruction has been completed, is proposed. Also, the performance of the scheme is examined using Simplescalar simulator for SPECint95 benchmarks in which our value predictor is added.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.2
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• pp.97-103
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• 2009

In this paper, the performance of a hybrid value predictor according to the instruction fetch rate on window size superscalar processors is evaluated. In general, the data dependency relations of instructions are increased with the number of the fetched instructions. Therefore, it is expected that the performance of a value predictor will be higher when the instruction fetch rate is increased. The performance is studied for the machine with collapsing buffer and he one with trace cache as an instruction fetch mechanism. As a result of experiment, it is showed that the performance effect of a value predictor is higher as the instruction fetch rate of instruction window size, IPC, predict rate on apply with non-tc and tc is increased.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.10
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• pp.569-578
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• 2003

Data dependencies are one of major hurdles to limit ILP(Instruction Level Parallelism), so several related works have suggested that the limit imposed by data dependencies can be overcome to some extent with use of the data value prediction. Hybrid value predictor can obtain the high prediction accuracy using advantages of various predictors, but it has a defect that same instruction has overlapping entries in all predictor. In this paper, we propose a new hybrid value predictor which achieves high performance by using the information of static and dynamic classification. The proposed predictor can enhance the prediction accuracy and efficiently decrease the prediction table size of predictor, because it allocates each instruction into single best-suited predictor during the fetch stage by using the information of static classification. Also, it can enhance the prediction accuracy because it selects a best- suited prediction method for the “Unknown”pattern instructions by using the dynamic classification mechanism. Simulation results based on the SimpleScalar/PISA tool set and the SPECint95 benchmarks show the average correct prediction rate of 85.1% by using the static classification mechanism. Also, we achieve the average correction prediction rate of 87.6% by using static and dynamic classification mechanism.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.592-600
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• 2001

To improve the performance of wide-issue Superscalar microprocessors, it is essential to increase the width of instruction fetch and issue rate. Data dependences are major hurdle to exploit ILP(Instruction-Level Parallelism) efficiently, so several related works have suggested that the limits imposed by data dependences can be overcome to some extent with the use of the data value prediction. But the suggested mechanisms may access the same value prediction table entry again before they have been updated with a real data value. They will cause incorrect value prediction by using stable data and incur misprediction penalty and lowering performance. In this paper, we propose a new hybrid value predictor which achieve high performance by reducing stale data. Because the proposed hybrid value predictor can update the prediction table speculatively, it efficiently reduces the number of mispredicted instruction due to stable due to stale data. For SPECint95 benchmark programs on the 16-issue superscalar processors, simulation results show that the average prediction accuracy increase from 59% for non-speculative update to 72% for speculative update.

• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2196-2203
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• 2000

As processor's operational frequency increases and processors execute multiple instructions per cycle, the processor performance becomes more dependent on the load operand referencing latency and the data dependency. To reduce the operand fetch latency and to increase ILP by breaking the data dependency, we propose a value-address hybrid predictor using a reasonable size prediction buffer and analyse the performance improvement by the proposed predictor. Through the extensive simulation of 5 benchmark programs, the proposed hybrid prediction scheme accurately predicts 62.72% of all loads which are 12.64% higher than the value prediction scheme and show its cost-effectiveness compared to the address predition scheme. In addition, we analyse the performance improvement achieved by the stride management and the history of previous predictions.

• Journal of the Korea Computer Industry Society
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• v.7 no.3
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• pp.171-178
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• 2006

Value prediction of instruction issue width in superscalar processor is a technique to obtain performance gains by supplying earlier source values of its data dependent instructions using predicted value of a instruction. In this paper, the mean performance improvement by predictor as well as prediction accuracy and prediction rate are moaned and assessed by comparison and analysis of value predictor that instruction issue width(4,8,16) in parallel and run by predicting value, which is for performance improvements of ILP[4]. The experiment result show the superiority hight performance of 8-issue.