• International Journal of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.122-128
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• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.653-660
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• 2001

In this paper, we designed 2303.15MHz frequency synthesizer for the purpose of the phase noise prediction. For the modeling of phase noise generated in the designed system through introducing the noise-modeling method suggested by Lascari we analyzed a variation of phase noise as according as that of offset frequency. Especially, for the third-order system of the PLL among some kinds of phase noise generated from VCO we analyzed the aspect of 1/f-noise appearing troubles in the low frequency band. Since it is difficult to analyze mathematically 1/f-noise in the third-order system of the PLL, introducing the concept of pseudo-damping factor has made an ease of the access of the 1/f-noise variance. we showed a numerical formula of 1/f-noise variance in the third-order system of the PLL which is compared with that of 1/f-noise variance in the second-order system of the PLL. As a result, In case of txco we found the reduce rapidly along the offset frequency after passed through that phase-noise was -160dBc/Hz before passed through a loop at 10kHz offset frequency and -162.6705dBc/kHz after passed through the loop, -180dBc/Hz at 100kHz offset frequency and -560dBc/kHz after passed through the loop. We can notice that the variance of third-order system more occurs (or the variance of second-order system in connection with noise bandwidth and variance factor of second-order and third-order system.

• Journal of Navigation and Port Research
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• v.27 no.4
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• pp.437-441
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• 2003

In this paper, the 30 W power amplifier for an IMT-2000 repeater was developed a gain flatness and the third IMD (Intermodulation distortion) by microwave absorber. The absorption ability of the absorber is shown up to -10 dB and -4 dB at 3.6 GHz, 2.3 GHz band, respectively. The power amplifier without absorber has the gain over 57 dB, the gain flatness of $\pm$0.33 dB and the third IMD of 27 dBc at 33.3 W output. Otherwise, the power amplifier with absorber has the gain over 58 dB, the gain flatness of less than $\pm$0.9, the third IMD over 29 dBc at the same output power. As a result, the characteristic of the different type shows improvement of 1 dB in gain, 0.3 dB in gain flatness and 1.77 dBc in IMD.

• Journal of electromagnetic engineering and science
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• v.5 no.1
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• pp.8-13
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• 2005

The InGaP/GaAs hetero-junction bipolar transistor(HBT) monolithic voltage-controlled dielectric resonator oscillator(VCDRO) is first demonstrated for a Ku-band low noise block down-converter(LNB) system. The on-chip voltage control oscillator core employing base-collector(B-C) junction diodes is proposed for simpler frequency tuning and easy fabrication instead of the general off-chip varactor diodes. The fabricated VCDRO achieves a high output power of 6.45 to 5.31 dBm and a wide frequency tuning range of ]65 MHz( 1.53 $\%$) with a low phase noise of below -95dBc/Hz at 100 kHz offset and -115 dBc/Hz at ] MHz offset. A]so, the InGaP/GaAs HBT monolithic DRO with the same topology as the proposed VCDRO is fabricated to verify that the intrinsic low l/f noise of the HBT and the high Q of the DR contribute to the low phase noise performance. The fabricated DRO exhibits an output power of 1.33 dBm, and an extremely low phase noise of -109 dBc/Hz at 100 kHz and -131 dBc/Hz at ] MHz offset from the 10.75 GHz oscillation frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1210-1218
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• 2001

In this paper, A X-band voltage-controlled hair-pin resonator oscillator(VCHRO) is able to a local oscillator or a signal source in transmitter/receiver of a microwave communication system for mobile radar, is designed and fabricated In order to apply mobile radar system is used the hair-pin resonator stronger on shock or vibration than the dielectric resonator, and also, in order to improvement the phase noise and output power is used a system of serial feedback format A hair-pin resonator was simulated by momentum method of HP ADS and then a oscillator circuit was designed that operates at 10.525 GHz by nonlinear method in harmonic balance simulation. The HRO generated output power of 6.93 dBm at 10.525 GHz, phase noise of -57.74 dBc at 100 kHz offset from carrier and the 2'nd harmonic was suppressed -23.90 dBc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.530-534
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• 2002

In the thesis, For improving the Stability of VCHRO(Voltage Controlled Hair-pin Resonator Oscillator) the new structure using the parallel feedback of the second harmonic is proposed for self-phase locking effect. This module is composed of wilkinson divider, frequency doubler, directional coupler, and bandpass filter using a hair-pin resonator, which are integrated into miniaturized hybrid circuit. The module exhibits output power of 2.5 dBm at 19.5 GHz, -29.83 dBc fundamental frequency suppression and -76.52 dBc/Hz phase noise at 10 kHz offset frequency from carrier of center frequency 19.5 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.1020-1027
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• 2005

In this paper, economic miniature RF transmitter module for intelligent transportation system(ITS) is described. This module which consists of ASK modulator, frequency synthesizer, power amplifier is operating at 5.8 GHz frequency band and implemented by using LTCC process technique. Thus, ultra small size of 0.8 CC and improved electrical performances has been obtained. From the test results, transmitting characteristics of 10 dBm ouput power and -46 dBc interchannel interference with 1.024 Mbps ASK modulated have been shown. Frequency synthesizer as a transmitting signal source reveals very short locking time of 26 usec and outstanding phase noise of -115 dBc/Hz at 1 MHz offset from 5.8 GHz center frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1117-1124
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• 2011

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. We improved frequency synthesizer performance of phase noise, resolution and spurious using the DDS driven hybrid method The proposed frequency synthesizer has the bandwidth of 1 GHz, frequency switching time of below 9 ${\mu}s$, suppressed spurious level of below -68.9 dBc. phase noise of -113.58 dBc/Hz at offset 100 kHz and flatness of ${\pm}$0.7 dB.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.215-220
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• 1999

In fabricated linear power amplifier(LPA), the third-order inter-modulation distortion(IMD) for main amplifier alone is 10.61dBc, and the IMD for LPA with predistorter and feedforward loop combined is 32.50dBc. Therefore, the IMD characteristic results an improvement of approximately 22dB. The main amplifier efficiency with single tone input is close to 30%, and the efficiency of the overall LPA with predistorter is 27.4% and predicted feedforward loop efficiency without predistorter is about 20%. Therefore, LPA with predistorter and feedforward loop combined is improved by 7.4%.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1444-1445
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• 2008

최근 Wireless Local Area Network(WLAN), Wide-band Code Division Multiple Access(WCDMA), CDMA2000, Bluetooth 등 다양한 모바일 통신 시스템에 대한 수요가 증가하고 있다. 이와 같은 모바일 통신 시스템에는 70dB이상의 SFDR(Spurious Free Dynamic Range)을 가진 ADC(Analog-to-Digital Converter)가 사용된다. 본 논문에서는 모바일 통신 시스템을 위한 SFDR 70dBc의 성능을 제공하는 10비트, 100Msps 파이프라인 ADC를 제안한다. 제안한 ADC는 요구되는 해상도 및 속도 사양을 만족시키기 위해 3단 파이프라인 구조를 채택하였으며, 입력단 SHA(Sample and Hold)회로에는 Nyquist 입력에서도 10비트 이상의 정확도로 신호를 샘플링하기 위해 부트스트래핑 기법 기반의 샘플링 스위치를 적용하였다. residue amplifier 회로에는 전력을 줄이기 위해 8배 residue amplifier 대신 3개의 2배 ressidue amplifier를 사용하였다. ADC의 높은 사양을 만족시키기 위해서는 높은 이득을 가지는 op-amp가 필수적이다. 제안한 ADC 는 0.18um CMOS 공정으로 설계되었으며, 100Msps의 동작 속도에서 70dBc 수준의 SFDR과 60dB 수준의 SNDR(Signal to Noise and Distortion Ratio)을 보여준다.