• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• Journal of Electrical Engineering and Technology
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• v.6 no.1
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• pp.48-58
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• 2011

In this paper, an attempt has been made to design the current and speed proportional and integral (PI) regulators of self-commutating current source inverter-fed induction motor drive having capacitors at the machine end and to investigate the transient performance of the same for step changes in reference speed. The mathematical model of the complete drive system is developed in closed loop, and the characteristic equations of the systems are derived using perturbation about steady-state operating point in order to develop the characteristic equations. The D-partition technique is used for finding the stable region in the parametric plane. Frequency scanning technique is used to confirm the stability region. Final selection of the regulator parameters is done by comparing the transient response of the current and speed loops for step variations in reference. The performance of the drive is observed analytically through MATLAB simulation.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.528-529
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• 2008

Proposed buck converter includes load current sensing circuit to compensate load regulation. Because error amp has finite gain, there is load regulation in SMPS. In this paper we use variable current source that is added to positive input of comparator and current of current source is changed by sensed load current. The simulation result shows that proposed buck converter has improved load regulation than conventional buck convertor.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.94-100
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• 2008

This paper presents a new control method of single-phase active power filter (APF) for the compensation of harmonic current components in nonlinear loads. To facilitate the possibility of complex calculation for harmonic current detection of the single phase, a single-phase system that has two phases was constructed by including an imaginary second-phase giving time delay to the load current. The imaginary phase, which lagged the load current T/4 (Here T is the fundamental cycle) is used in the conventional method. But in this proposed method, the new signal as the second phase is delayed by the filter. Because this control method is applied to a single-phase system, an instantaneous calculation was developed by using the rotating reference frames synchronized to source-frequency rather than by applying instantaneous reactive power theory that uses the conventional fixed reference frames. The control scheme of single-phase APF for the current source with R-L loads is applied to a laboratory prototype to verify the proposed control method.

• Journal of the Korean Society of Industry Convergence
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• v.10 no.4
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• pp.227-233
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• 2007

In case of design of a rectifier to supply high current, To select switching frequency of semiconductor switches affect absolutely the design of the LC filter value in an power conversion circuit. The conventional rectifier by using MOSFET is no use in high current equipments because of small drain-source current. To solve this problem, this paper proposes to design of high capacity rectifier by parallel driving of MOSFET in the single half bridge DC-DC converter. This method can be able to develop high current rectifier by distributed drain-source current. The proposed scheme is able to expect a decrease in size, weight and cost of production by decreasing the LC filter value and increasing maximumly the switching frequency. The validity of the proposed parallel driving strategy is verified through computer-aided simulations and experimental results.

• Progress in Superconductivity and Cryogenics
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• v.4 no.1
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• pp.110-113
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• 2002

The high-tc superconducting fault current limiters (SFCL) are studied worldwide to be classified as resistive type or inductive type such as magnetic shielding type and dc reactor type. This Paper deals with an open core type SFCL, a kind of magnetic shielding type SFCL. We manufactured a 30 kVA open core type SFCL. It was modified from the old one with a rated power of 8 kVA. We stacked four superconducting tubes as magnetic shielding material and used the same primary winding as the old one. The experiments were performed with a maximum source voltage of 1 kV. The results show that the fault current in the source voltage of 1 kVrms was reduced to be about 105 Apeak, which was calculated to be about 22 % of the fault current in the system without an SFCL.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.729-733
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• 2003

This paper proposed a novel current control strategy on active power filters using p-q-r instantaneous power theory which can compensate the line current harmonics and the neutral line current in unbalanced and/or distorted source conditions in three-phase four-wire systems. The proposed current control method is based on a sinusoidal PWM for fully-digital implementation which was compared with a hysteresis PWM. Simulation results showed good performance of the proposed current control strategy on shunt type APFs.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.211-213
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• 1994

In tins paper, the method of analysis of induction heating is proposed. It's a coupled problem. First, eddy current problem with current source is analyzed using 2-D finite element method, from which eddy current distribution is obtained. And the second, heat source can be calculated directly by the eddy current. Also the temperature distribution is obtained using 2-D finite element method. Eddy current problem and heat transfer problem are dealt with under steady state in this paper.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1333-1335
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• 2000

In order to turn on the SCR gate, trigger signal source have to provide appropriate gate current and voltage under the gate rating based on the characteristic of SCR, the nature of load and power. It will be essential design factors such as trigger source impedance, trigger signal occurring, signal time width and turn off conditions. Also minimum gate trigger current is changed with the deterioration of SCR. SCR, which is needed large gate trigger current absolutely, is very important for SCR characteristic test because it causes unstable output in the misfile or makes a trouble to pulse trigger circuits. This paper shows scheme to test the performance of SCR with the precision analyzing mechanism and the changing trend of minimum gate current under the trigger conditions.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2531-2533
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• 2001

This paper describes a low noise and high efficiency analog-digital switching mixed mode battery charger for production facilities of Li-Ion batteries. The requirements for battery chargers for production facilities are very strict. The accuracy of output voltage and output current should be below 0.1% with very low ripple current. Therefore analog type linear regulators are widely used for battery charger in spite of their inefficiency and bulkiness. We combined linear regulator as a voltage source with digital switching converter as a dependent current source. Low current ripple and high accuracy are obtained by linear regulator while high efficiency is achieved by digital switching converter. Experimental results show that proposed method has 0.1% ripple and 90% efficiency at an output current of 1A for a battery voltage of 4V.