• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.116-121
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• 2005

To realize the tap coefficient of a finite impulse response(FIR) filter or the twiddle factor of a fast Fourier transform(FFT) using a current-mode analog circuit, a high accurate current-attenuator circuit is needed This paper introduces an accuracy enhancement technique in the current-mode signal processing. First of all, the DC of set-current error in a conventional current-attenuator using a gate-ratioed orient mirror circuit is analyzed and then, the current-attenuator circuit with a negligibly small DC offset-current error is introduced. The circuit consists of N-output current mirrors connected in parallel with me another. The output current of the circuit is attenuated to 1/N of the input current. On the basis of the Kirchhoff current law, the current scale ratio is determined simply by the number of the current mirrors in the N-current mirrors connected in parallel. In the proposed current-attenuator circuit the scale accuracy is limited by the ac gain error of the current mirror. Considering that a current mirror has a negligibly small ac gain error, the attainable maximum scale accuracy is theoretically -80[dB] to the input current.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.1-9
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• 1997

Novel class A CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well standard CMOS process for high-frequency current-mode signal processing were developed. The CCII consists of a regulated current-cell for the voltage input and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated cCII show that the current input impedance is 308 .ohm. and the 3-dB cutoff frequency when used as a voltage amplifier extends beyond 10MHz. The linear dynamic ranges of voltage and current are from -0.5V to 1.5V and from -100.mu.A to +120.mu.A for supply voltage V$\_$DD/ = -V$\_$SS/=2.5V, respectively. The power dissipation is 2 mW and the active chip area is 0.2 * 0.2 [mm$\^$2/].

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.179-187
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• 2008

In this paper, we carried out the performance evaluation of depolarized fiber optic gyroscope(D-FOG) that was designed and fabricated with the low-cost optical communication single mode fiber and depolarizer. In order to reduce the phase error of D-FOG, the circuit of stabilized current and temperature of the light source was made and the performance was analyzed. The current and the temperature stability of the fabricated stabilization circuit were less than $200{\mu}A$ and $0.0098^{\circ}C$, respectively. Also, the D-FOG's experimental result showed that the value of the dynamic range of rotated rate, the scale factor error with a good linearity, and the zero bias drift were ${\pm}50^{\circ}/s$, 2.8881%, and $19.49^{\circ}/h$, respectively. The results indicated that a low-cost FOG was able to fabricate which was more cost effective than conventional FOG with a high-cost high-birefringent polarization maintaining fiber.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.19-26
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• 1997

Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].

• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.106-113
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• 1997

A 3V CMOS continuous-time fully-balanced integrator for low-voltage analog-digital mixed-mode signal processing is designed in this paper. The basic architecture of the designed fully-balanced integrator is complementary circuit which is composed of NMOS and PMOS transistor. And this complementary circuit can extend transconductance of an integrator. So. the unity gain frequency, pole and zero of integrator are increased by the extended transconductance. The SPICE simulation and small signal analysis results show that the UGF, pole and zero of the integrator is increased larger than those of the compared integrtors. The three-pole active low-pass filter is designed as a application circuit of the fully-balanced integrator, using 0.83V CMOS processing parameter.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.119-127
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• 2011

The paper surveys various analytical models for IEEE 802.11 medium access control protocols and critically discusses recent issues developing in wireless mobile ad hoc networks and their MACs. The surveyed MAC protocols include the standard IEEE 802.11 MAC suites such as IEEE 802.11 DCF, IEEE 802.11 PCF, IEEE 802.11e EDCA, and IEEE 802.11 ad hoc mode; and also the newer, de facto MAC protocols. We study the analytic models of the standard MAC suites followed by the newer analytic models that have been published in recent years. Also, the paper tries to include most of current literatures discussing analytic modeling of MAC in conjunction to some critical issues such as contention among ad hoc nodes, hidden terminal problems, and real-time service support.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.22-29
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• 1998

In this paper, an 10 bit current-mode CMOS A/D converter with a current predictor is designed with a CMOS process to be integrated into a portable image signal processing system. A current predictor let the number of comparator reduce to 70 percent compared with the two step flash architecture. The current magnitude of current reference is reduced to 68 percent with a modular current reference. The designed 10 bit Low-power current-mode CMOS A/D converter with a current predictor is simulated with HSPICE using 0.6$\mu\textrm{m}$ N-well single-poly triple-metal CMOS process parameters. It results in a conversion rate of 10MSamples/s. A power consumption is measured to be 94.4mW at single +5V supply voltage. The 10 bit A/D converter fabricated using the same process occupies the chip area of 1.8mm x 2.4mm.

• Current Optics and Photonics
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• v.2 no.2
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• pp.134-139
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• 2018

A novel approach for frequency-tripling vector signal generation via balanced detection without precoding and optical filter is proposed. The scheme is mainly utilizing an integrated dual-polarization quadrature phase shift keying (DPQPSK) modulator. In the DPQPSK modulator, one QPSK modulator is driven by an RF signal to generate high-order optical sidebands, while the other QPSK modulator is modulated by I/Q data streams to produce baseband vector signal as an optical carrier. After that, a frequency-tripling 16-quadrature-amplitude-modulation (16QAM) vector millimeter-wave (mm-wave) signal can be obtained by balanced detection. The proposed scheme can reduce the complexity of transmitter digital signal processing. The results show that, a 4 Gbaud baseband 16QAM vector signal can be generated at 30 GHz by frequency-tripling. After 10 km single-mode fiber (SMF) transmission, the constellation and eye diagrams of the generated vector signal perform well and a bit-error-rate (BER) below than 1e-3 can be achieved.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.12
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• pp.7287-7291
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• 2014

A CDTA (current differencing transconductance amplifier) is an active building block for current mode analog signal processing with the advantages of high linearity and a wide frequency bandwidth. In addition, it can generate a stable voltage because all the differencing input current flows to the grounded devices. In this paper, a new small signal equivalent circuit is proposed to analyze a CDTA. The proposed small signal equivalent circuit provides greater precision in analyzing the magnitude and frequency response than its previous counterparts because it considers the parasitic components of the input, internal and output terminal. In addition, observations of the changes made in various devices, such as the resistor (Rz) confirmed that those devices heavily influence the characteristics of CDTA. The designed parameters of the proposed small signal equivalent circuit of the CDTA provides convenience and accuracy in the further design of analog integrated circuits. For verification purposes, a 2.5 MHz low pass filter was designed on the HSPICE simulation program using the proposed small signal equivalent circuit of CDTA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.93-103
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• 2002

A new current mirror for high-accuracy current-mode signal processing and integrated circuit design was proposed. The current mirror adopts the technique of an adaptive feedback to reduce the input impedance and the output stage of regulated cascode current mirror to increase the output impedance. Simulation results show that the current mirror has input impedance of 0.9Ω, the output impedance of 415 MΩ, and current gain of 0.96 at the supply voltage Vcc=5V. The power dissipation is 1.5㎽. In order to certify the applicability of the proposed current mirror, a voltage-to-current converter using the current mirror is designed. Simulation results show that the converter has good agreement with theoretical equation and has three times better conversion characteristics when compared with voltage-to-current converter using Wilson current mirror.