• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• Journal of the Korean Solar Energy Society
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• v.30 no.6
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• pp.102-107
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• 2010

a-Si solar cell has relatively dominant drift current when compared with crystalline solar cell due to the high internal electric field. Such drift current make an impact on the PV module in the local shading. In this paper, the a-Si PV module output characteristics of shading effects was approached in terms of process condition, because of the different deposition layer of thin film lead to rising the resistance. We suggested design condition to ensure the long-term durability of the module with regard to the degradation factors such as hot spot by analyzing the module specification. The result shows a remarkable difference on module uniformity for each shading position. In addition, the unbalanced power loss due to power mismatch of each module could intensify the degradation.

• Korean Journal of Schizophrenia Research
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• v.20 no.1
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• pp.15-22
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• 2017

Objectives : It has been shown that early intervention is crucial for favorable outcome in patients with schizophrenia. However, development of biomarkers for predicting prognosis of psychotic disorder still requires more research. In this study, we aimed to investigate whether baseline mismatch negativity (MMN) predict prognosis in patients with first episode psychosis (FEP). Methods : Twenty-four patients with FEP and matched healthy controls (HCs) were examined with MMN at baseline, and their clinical status were re-assessed after 1 year. Repeated-measures analysis of variance was performed to compare baseline MMN between the two groups. Multiple regression analysis was used to identify factors predicting prognosis in FEP patients during the follow-up period. Results : MMN amplitudes at baseline were significantly reduced in patients with FEP compared to healthy controls. In the multiple regression analysis, baseline MMN amplitude significantly predicted later improvement of performances on digit span and delayed recall of California Verbal Learning Test. However, baseline MMN did not predicted improvement of clinical symptoms. Conclusion : These results indicate that MMN may be a possible predictor of improvement in cognitive functioning in patients with FEP. Future study with larger sample and longer follow-up period would be needed to confirm the findings of the current study.

• Journal of Power Electronics
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• v.17 no.2
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• pp.389-397
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• 2017

A control scheme for stand-alone inverters that utilizes an inductor current observer (ICO) is proposed. The proposed method measures disturbance load currents using a current sensor and it estimates the inductor current using the ICO. The filter parameter mismatch effect is analyzed to confirm the ICO's controllability. The ICO and controllers are designed in a continuous-time domain and transferred to a discrete-time domain with a digital delay. Experimental results demonstrate the effectiveness of the ICO using a 5-kVA single-phase stand-alone inverter prototype. The experimental results demonstrate that the observed current matches the actual current and that the proposed method can archive a less than 2.4% total harmonic distortion (THD) sinusoidal output waveform under nonlinear load conditions.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1929-1932
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• 2002

In this paper, some parameters are studied for the performance improvement of a bulk optical current sensor. The performance of optical current sensor is influenced by current measuring range, Verdet constant change due to temperature change, temperature variation of wave plate, signal to noise ratio of optical transmitter/receiver, optical bias mismatch. Two types of optical current sensors are implemented and tested in the current range from 10 ampere to 200 ampere.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.518-521
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• 1998

This paper describes a 3.3V-65MHz 12BIT CMOS current-mode DAC designed with a 8 MSB current matirx stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch ahs been employed. The simulation results of the designed DAC show a coversion rate of 65MHz, a powr dissipation of 71.7mW, a DNL of .+-.0.2LSB and an INL of .+-.0.8LSB with a single powr supply of 3.3V for a CMOS 0.6.mu.m n-well technology.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1582-1590
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• 2019

A new method for reducing the common-mode current generated by the voltage variations in a two-inverter air conditioner system by applying a synchronized pulse-width modulation (PWM) strategy is proposed. The PWM signals of the master-mode inverter are generated based on the reference voltage, while those of the slave-mode inverter are output in the opposite direction when the master-mode inverter changes its switching state. However, the slave-mode control results in a mismatch between the reference voltage and the actual output voltage that is modified by synchronized control operation. The proposed method is capable of reducing and controlling this voltage error by performing signal selection in the vector space of the slave-mode inverter, which mitigates the distortion of the phase current. The efficacy of this method in reducing conducted emissions has been validated both theoretically and experimentally.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.174-183
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• 1998

A simple and robust digital current control technique for a permanent magnet (PM) synchronous motor under the parameter variations is presented. Among the various current control schemes for an inverter-fed PM synchronous motor drive, the predictive control is known to give a superior performance. This scheme, however, requires the full knowledge of machine parameters and operating conditions, and cannot give a satisfactory response under the parameter mismatch. To overcome such a limitation, the disturbances caused by the parameter variations will be estimated by using a disturbance observer theory and used for the computation of the reference voltages by a feedforward control. Thus, the steady-state control performance can be significantly improved with a relatively simple control algorithm, while retaining the good characteristics of the predictive control. The proposed control scheme is implemented on a PM synchronous motor using the software of DSP TMS320C30 and the effectiveness is verified through the comparative simulations and experiments.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.185-185
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• 2008

This paper describes the broadband SDC (Single-ended to Differential Converter) for Digital Video Broadcasting-Satellite $2^{nd}$ edition (DVB-S2) receiver tuner IC. It is fabricated by using $0.18{\mu}m$ CMOS process. In order to obtain high linearity and low phase mismatch, the broadband SDC (Single-ended to Differential Converter) is designed with current mirror structure and cross-coupled capacitor and current source binding differential structure at VDD. The simulation result of SDC shows IIP3 of 11.9 dBm and IIP2 of 38 dBm. It consumes 5mA current with 2.7V supply voltage.