• 전기의세계
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• v.30 no.11
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• pp.734-746
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• 1981

This paper suggests on-load torque measurement for 3 phase induction motors by input -voltage and current utilizing symmetric coordinate analysis technique on the basis of the induction motor equivalent circuit. In this paper, two cases are treated with, i.e, one is the case where the motors' exciting current and primary leakage impedance voltage drop are compensated automatically, adopting the ideal wattmeter whose current coil impedance and voltage coil impedance are 0 and .inf. respectively, and the other is the case where non-ideal wattmeter is adopted and the compensation above is made by computation. As a result of the case study, following conclusions are obtained. 1) By proper combination of the error propagation law and the limit of power consumption, the desirable overall measurement error of the apparatus can be obtained on the basis of the inherent errors of CT and PT. 2) The measurement error is larger in current simulation circuit than in voltage simulation circuit. 3) Between the two cases, the latter is more advantageous than the former from the viewpoint of feasibility and the measurement error. 4) As the attachment of Ammeter in the current simulation circuit influences the measurement error considerably, its internal impedance should be large considerably. 5) The larger the consumption power of the apparatus is, the easier the feasibility is.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.3
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• pp.232-239
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• 2013

This paper proposes an improved stator flux estimator through ensuring conventional PLPF to act as a pure integrator for sensorless control of induction motors. Conventional PLPF uses the estimated synchronous speed as a cut-off frequency and has the gain and phase compensators. The gain and phase compensators are determined on the assumption that the estimated synchronous angular speed is coincident with the real speed. Therefore, if the synchronous angular speed is not same as the real speed, the gain and phase compensation will not be appropriate. To overcome the problem of conventional PLPF, this paper analyzes the relationship between the synchronous speed error and the phase lag error of the stator flux. Based on the analysis, this paper proposes the synchronous speed error compensation scheme. To achieve a start-up without speed sensor, the current model is used as the stator flux estimator at the standstill. When the motor starts up, the current model should be switched into the voltage model. So a stable transition between the voltage model and the current model is required. This paper proposes the simple transition method which determines the initial values of the voltage model and the current model at the transition moment. The validity of the proposed schemes is proved through the simulation results and the experimental results.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.2
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• pp.215-225
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• 1994

In this paper, a performance evaluation of different current regulators for induction motor drive systems fed by IGBT inverter is presented. The twoparts of current regulation are considered : current error compensation part, voltage modulation part. The characteristics of hysteresis, synchronous PI, decoupled PI, predictive, deadbeat and stage feedback controllers are analyzed and the steady-state performances and transient responses of current regulation are well compared through the simulation and experimental results.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Journal of Power Electronics
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• v.7 no.3
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• pp.238-245
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• 2007

This paper considers the problem of regulating the output voltage of a current doubler rectified asymmetric half-bridge (CDRAHB) DC/DC converter via fuzzy integral control. First, we model the dynamic characteristics of the CDRAHB converter with the state-space averaging method, and after introducing an additional integral state of the output regulation error, we obtain the Takagi-Sugeno (TS) fuzzy model for the augmented system. Second, the concept of parallel distributed compensation is applied to the design of the TS fuzzy integral controller, in which the state feedback gains are obtained by solving the linear matrix inequalities (LMIs). Finally, numerical simulations of the considered design method are compared to those of the conventional method, in which a compensated error amplifier is designed for the stability of the feedback control loop.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.3
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• pp.81-89
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• 2002

The sensorless AC motor drive is a popular topic of study due to the cost and reliability of speed and position sensors. Most sensorless algorithms are based on the mathematical modeling of motors including electrical variables such as phase current and voltage. Therefore, the accuracy of such variables largely affects the performance of the sensorless AC motor drive. However, the output voltage of the SVPWM-VSI, which is widely used in sensorless AC motor drives, has considerable errors. In particular, the SVPWM-VSI is error-prone in the low speed range because the constant DC link voltage causes poor resolution in a low output voltage command and the output voltage is distorted due to dead time and voltage drop. This paper investigates a novel high-performance strategy for overcoming these problems in a sensorless ac motor drive. In this paper, a variation of the DC link voltage and a direct compensation for dead time and voltage drop are proposed. The variable DC link voltage leads to an improved resolution of the inverter output voltage, especially in the motor's low speed range. The direct compensation for dead time and voltage drop directly calculates the duration of the switching voltage vector without the modification of the reference voltage and needs no additional circuits. In addition, the proposed strategy reduces a current ripple, which deteriorates the accuracy of a monitored current and causes torque ripple and additional loss. Simulation and experimentation have been performed to verify the proposed strategy.

• The Journal of Engineering Geology
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• v.25 no.4
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• pp.525-532
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• 2015

After comparing the effectiveness of standoff compensation between current techniques using data obtained from a series of borehole model experiments for standoff compensation in 2007, 2008, and 2009, a follow-up study was conducted to find a more effective standoff compensation algorithm, Comparing the results of the application of the conventional spine and ribs technique, and the spine and ribs technique in terms of apparent density shows that the standoff compensation error obtained from the latter method is more than twice that obtained from the former. The larger size of the compensation error from the spine and ribs plot using the radioactive decay equation indicates that there are no benefits in using this equation in standoff compensation. Based on these results, we propose a reverse transform spine and ribs technique by essentially combining the conventional spine and ribs technique and the spine and ribs technique in terms of apparent density.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.11
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• pp.493-497
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• 2005

This paper dealt with the influence of harmonic voltages on arrester diagnostics and its compensation method by using a designed Pspice arrester model. A pure sinusoidal voltage and its 3$^{rd}$ harmonic voltage were applied to the model, and the leakage current components were analyzed. The simulation results have shown that the peak value of resistive leakage current depends not only on the phase of the 3$^{rd}$ harmonic voltage but also on the magnitude of it. In this paper, an approximated 5$^{th}$ order polynomial formula by the Least-Square-Technique was derived, and correction factors which compensate the error caused by the 3$^{rd}$ harmonic voltage were calculated.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.610-617
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• 2011

This paper proposes a novel and direct dead-time compensation method of the 3-phase inverter using space vector pulse width modulation(SVPWM) topology. The proposed dead-time compensation method directly compensates the dead-time to the turn-on time of the effective voltage vector according to the current direction of the medium voltage reference. Each phase voltages are determined by the switching times of the effective voltage vectors, and the practical switching times have loss according to the current direction by the dead-time effect in the 3-phase inverter. The proposed method adds the dead-time to the switching time of the effective voltage vector according to the current direction, so it does not require complex d-q transform and controller to compensate the voltage error. The proposed dead-time compensation scheme is verified by the computer simulation and experiments of 3-phase R-L load.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.