• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.164-167
• /
• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.1
• /
• pp.143-152
• /
• 2012

In this paper hardware implementation of GF($2^{191}$) elliptic curve cryptographic coprocessor which supports 7 operations such as scalar multiplication(kP), Menezes-Vanstone(MV) elliptic curve cipher/decipher algorithms, point addition(P+Q), point doubling(2P), finite-field multiplication/division is described. To meet structure resistant against simple power analysis, the ECC processor adopts the Montgomery scalar multiplication scheme which main loop operation consists of the key-independent operations. It has operational characteristics that arithmetic units, such GF_ALU, GF_MUL, and GF_DIV, which have 1, (m/8), and (m-1) fixed operation cycles in GF($2^m$), respectively, can be executed in parallel. The processor has about 68,000 gates and its simulated worst case delay time is about 7.8 ns under 0.35um CMOS technology. Because it has about 320 kbps cipher and 640 kbps rate and supports 7 finite-field operations, it can be efficiently applied to the various cryptographic and communication applications.

• Journal of IKEEE
• /
• v.22 no.2
• /
• pp.233-241
• /
• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.8
• /
• pp.1741-1748
• /
• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.6 no.3
• /
• pp.381-387
• /
• 2011

Measurement controller that acquire and control and observe data from scattering sensors is organic with central control room. Therefore, measurement controller is efficient wireless network than wire network. But, serious problem is happened in security from outside if use wireless network. Therefore, this paper proposed suitable MS-WP cryptographic system to measurement control wireless network to augment network efficiency of measure controller. Result that implement proposed MS-WP cryptographic system by chip level and achieve a simulation, confirmed that 130% processing rate increase and system efficiency are increased double than AES algorithm. Proposed MS-WP cryptographic system augments security and is considered is suitable to measurement controller because that low power is possible and the processing speed is fast.

• Journal of Advanced Navigation Technology
• /
• v.28 no.1
• /
• pp.142-148
• /
• 2024

It is difficult to apply authentication methods of existing wired or wireless networks to Internet of Things (IoT) devices due to their poor environment, low capacity, and low-performance processor. In particular, there are many problems in applying methods such as blockchain to the IoT environment. In this paper, edge computing is used to serve as a server that authenticates disposable templates among biometric information in an IoT environment. In this environment, we propose a lightweight and strong authentication procedure using the IoT-edge computing (IoT-EC) system based on elliptic curve cryptographic (ECC) and evaluate its safety.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.674-677
• /
• 2002

This paper describes the design of elliptic curve crypto (ECC) coprocessor over binary fields for ECC protocols. Our ECC processor provides the elliptic curve operations for Diffie-Hellman, EC Elgamal and ECDSA protocols. The ECC we have implemented is defined over the fieTd GF(2$\^$163/),which is a SEC-2 recommendation［6］.

• Proceedings of the Korean Information Science Society Conference
• /
• 2004.10a
• /
• pp.406-408
• /
• 2004

인터넷 보안에 대한 중요성이 나날이 증가하고 있으며. 이러한 인터넷 보안 문제의 해결책으로 개발된 IPSec은 IP 계층에서 보안서비스를 제공하기 위하여 AH와 ESP를 사용하여 보안연계(Security Association) 서비스를 제공한다. 본 논문에서는 32-bit 데이터 베이스를 이용하여 새로운 AES로 채택된 Rijndael 암호 알고리즘과 HMAC-SHA-1 인증 알고리즘을 통합시킨 IPSec 암호 프로세서를 구현하였다. Xilinx ISE 5.2i를 사용하여 VHDL로 설계하였고, ModelSim으로 시뮬레이션 검증을 수행하였으며, Xilinx사의 Vertex XCV1000E로 구현하였다. 본 논문에서 구현한 IPSec 암호 프로세서는 WLAN이나 VPN, Firewall등에 응용될 수 있을 것이다.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.521-524
• /
• 2004

For implementation of Cryptographic algorithms, security against implementation attacks such as side-channel attacks as well as the speed and the size of the circuit is important. Power Analysis attacks are powerful techniques of side-channel attacks to exploit secret information of crypto-processors. In this thesis the FPGA implementation of versatile elliptic crypto-processor is described. Explain the analysis of power consumption of ALTERA FPGA(FLEX10KE) that is used in our hand made board. Conclusively this thesis presents clear proof that implementations of Elliptic Curve Crypto-systems are vulnerable to Differential Power Analysis attacks as well as Simple Power Analysis attacks.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.6
• /
• pp.1075-1082
• /
• 2017

This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.