• Journal of Advanced Navigation Technology
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• v.12 no.2
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• pp.146-153
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• 2008

Due to the extremely short pulse in the Ultra-Wideband (UWB) technology, the accurate synchronization acquisition method is very important for both high data-rate WPAN and low data-rate WPAN. In this paper, we propose the synchronization acquisition algorithm based on two-step signal search method to acquire the synchronization in the UWB multi-path channel. At the first step, the search window is divided by two and the window that has higher power is chosen as a next search window. This operation is repeated until the measure power of the search window is smaller than the threshold value. At the second step, we employ Linear Search algorithm to the search window obtained at the first step for fine search. The proposed algorithm is proved that the synchronization acquisition is faster than the parallel search algorithm and it shows good performance in environment of the SNR extreme changes by the simulation.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.2
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• pp.77-83
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• 2011

In this paper, we present the design procedure of the synchronizer and the demodulator of a 13.56MHz RFID PJM tag, which was standardized in ISO 18000-3 mode 3. We optimize the algorithms in order to minimize the number of registers and implement them based on international standard. The designed module is simulated by Modelsim and FPGA. The synchronizer is composed of 3 correlators that is implemented by 1,024(16bit ${\times}$ 64cycle) registers. The demodulator is composed of 2 correlators that is implemented by 128(2bit ${\times}$ 64cycle) registers. The simulation performed with the demodulator integrated with the synchronizer shows that it works at about 87% success rate with the test data of SNR -2dB and 100% with those of SNR 4dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.8C
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• pp.742-753
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• 2005

In this paper, we propose a rapid and reliable signal acquisition scheme for UWB (Ultra Wide Band) systems in typical indoor wireless channels. The proposed scheme is a two-step search with different thresholds and search window applied to a single correlator, where each step utilizes the single-dwell search with the bit reversal. Simulation results in IEEE 802. I5 Task Group .3a UWB indoor wireless channel show that the proposed scheme for the LHWB signals can achieve significant reduction of the required mean acquisition time as compared to the conventional single-dwell bit reversal search and double-dwell bit reversal search with more complex structure employing two correlators for various threshold levels. In addition, it is also observed that the proposed scheme can achieve much faster and reliable signal acquisition in noisy environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.31-36
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• 2004

In this paper, we proposed the new structure of the Rake Finger using Walsh Switch, the shared accumulator, and the pipeline-FWHT algorithm for reducing the signal processing complexity resulting from the increase of the number of data correlator. The function simulation of the proposed architecture is performed by Synopsys tool and the timing simulation is performed by Compass tool. The number of computational operation in the proposed data correlators is 160 additions and the conventional ones is 512 additions when the number of walsh code N=4. As a result, it is reduced about 3.2 times other than the number of computational operation of the conventional ones. Also, the result shows that the data processing time of the proposed Rake Finger architecture is 90,496[ns] and the conventional ones is 110,696[ns]. It is $18.3\%$ faster than the data processing time of the conventional Rake Finger architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.31-37
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• 2009

This paper presents an efficient frame synchronization strategy with the identification of modulation type for Digital Video Broadcasting-Satellite second generation (DVB-S2). To detect the Start Of Frame (SOF) and identify a modulation mode at low SNR, we propose a new correlator structure and a low complexity Automatic Gain Controller (AGC). The proposed frame synchronization architecture can reduce about 93% multipliers and 89% adders compared with the direct implementation of the Differential - Generalized Post Detection Integration (D-GPDI) algorithm which is very complex and the proposed a low complexity AGC consists of only 5 multipliers and 3 adders. The proposed architecture has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Journal of Positioning, Navigation, and Timing
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• v.6 no.1
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• pp.17-26
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• 2017

Latency occurs in RTK, where the measured position actually outputs past position when compared to the measured time. This latency has an adverse effect on the navigation accuracy. In the present study, a system that estimates the latency of RTK and compensates the position error induced by the latency was implemented. To estimate the latency, the speed obtained from an odometer and the speed calculated from the position change of RTK were used. The latency was estimated with a modified correlator where the speed from odometer is shifted by a sample until to find best fit with speed from RTK. To compensate the position error induced by the latency, the current position was calculated from the speed and heading of RTK. To evaluate the performance of the implemented method, the data obtained from an actual vehicle was applied to the implemented system. The results of the experiment showed that the latency could be estimated with an error of less than 12 ms. The minimum data acquisition time for the stable estimation of the latency was up to 55 seconds. In addition, when the position was compensated based on the estimated latency, the position error decreased by at least 53.6% compared with that before the compensation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.19-25
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• 2004

In this paper, we propose optimal and suboptimal serial code acquisition schemes for chip-asynchronous direct-sequence spread-spectrum systems. The conventional serial code acquisition scheme is to compare each value of correlator outputs with a threshold individually. However, such a scheme is optimum only under the chip-synchronous assumption which is actually very difficult to be held prior to acquisition at the receiver because the signal-to-noise ratios before despreading are very low. In this paper, an optimal serial code acquisition scheme is derived based on the maximum-likelihood criterion under the more realistic and general chip-asynchronous environments. A suboptimal scheme, which is simpler but yields comparable performance to the optimal one, is also derived based on the criterion of local detection power Numerical results show that, under the chip-asynchronous environments, both the optimal and suboptimal serial code acquisition schemes outperform the conventional serial code acquisition scheme.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.6
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• pp.505-514
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• 2014

The effects of reflected wave of the sea on pseudolite ranging accuracy are analysed in this paper, when a pseudolite navigation system is used for wide area outdoor applications such as aircraft and vessels positioning. Methods for minimizing the influence of sea surface reflection wave were proposed. The methods include the appropriate correlator in pseudolite navigation system through the correlation performance comparison analysis in receiver design, the use of the technology of multiple antennas, and locating the transmitting station antenna on an appropriate position. From the results of experiments, the method of locating the antenna position shows the most reliable performance against the effect of surface reflection wave. The analysis results of the ranging accuracy improvement are addressed, when the multipath caused by sea surface reflection exists.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• Publications of The Korean Astronomical Society
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• v.24 no.1
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• pp.65-81
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• 2009

We present the performance test results of VLBI Correlation Subsystem (VCS) trial product which was being developed for 1 year from August 2007. It is a core component of Korea-Japan Joint VLBI Correlator (KJJVC). The aim for developing VCS trial product is to improve the performance of VCS main product to reduce the efforts and cost, and to solve the design problems by performing the preliminary test of the manufactured trial product. The function of VCS trial product is that it is able to process the 2 stations-1 baseline, 8 Gbps/station speed, 1.2 Gbps output speed with FX-type. VCS trial product consists of Read Data Control Board (RDC), Fourier Transform Board (FTB), and Correlation and Accumulation Board (CAB). Almost main functions are integrated in the FTB and CAB board. In order to confirm the performance of VCS trial product functions, the spectral analysis, delay compensation and correlation processing experiments were carried out by using simulation and real observation data. We found that the overflow problem of re-quantization after FFT processing was occurred in the delay compensation experiment. We confirmed that this problem was caused by valid bit-expression of the re-quantized data. To solve this problem, the novel method will be applied to VCS main product. The effectiveness of VCS trial product has been verified through the preliminary experimental results, but the overflow problem was occurred.