• 연구논문집
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• s.33
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• pp.17-25
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• 2003

In this work, thermal design of a PCR chip for LOC is systematically conducted. From the numerical simulation of a PCR chip based on the finite volume method, how to control the average temperature of a PCR chip and the temperature difference between the denaturation zone and the annealing zone is presented. The average temperature is shown to be controlled by adjusting heat input and a cooler as well as a heater is shown to be necessary to obtain three individual temperature zones for polymerase chain reaction. To reduce the time required, a heat sink for the cooler is not included in the calculation domain for the PCR chip and heat sink design is conducted separately by using a compact modeling method, the porous medium approach.

• Journal of the Korean Society for Heat Treatment
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• v.33 no.6
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• pp.296-302
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• 2020

Magnesium alloys have been rapidly attracting as lightweight structural material in various industry fields because of having high specific strength and low density. It is well known that the crystallographic texture plays an important role in improvement of poor room temperature ductility of magnesium alloys. In this study, high-temperature plane strain compression deformation was conducted on extruded AZ80 magnesium alloy at 723K by varying the strain rates ranging from 5.0×10^-3s^-1 to 5.0×10^-2s^-1 in order to investigate the behaviors of texture formation. It was found that texture formation behaviors in three kinds of specimens were affected by continuous and discontiuous deformation mechanism.

• Journal of Hydrogen and New Energy
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• v.30 no.5
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• pp.455-464
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• 2019

Experiments were conducted to investigate the sensitivity of steel plate oxidation with temperature in a simulated furnace. Used steel plates were a general steel and a high tensile steel. Porous media burner (PM burner) used in model furnace was made for uniform temperature profile. The surrounding temperature was controlled by adjusting the flow rate of the mixture in the combustor. Oxide layer analysis was performed using SEM image analysis and EDS line scanning. Both steel sheets showed a tendency to increase the thickness of the steel sheet surface oxide layer as the temperature increases, and it was confirmed that the flaking phenomenon in surface oxidation layer appeared when the temperature was above a certain temperature.

• Korean Journal of Metals and Materials
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• v.46 no.1
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• pp.39-43
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• 2008

PSII (Plasma Source Ion Implantation) using high density pulsed ICP source was employed to implant oxygen ions in Si wafer. The PSII technique can achieve a nominal oxygen dose of $3 {\times}10^{17}atoms/cm^2$ in implantation time of about 20min. In order to prevent oxidation of SOI layer during high temperature annealing, the wafer was capped with $2,000{\AA}$ $Si_3N_4 $ by PECVD. Cross-sectional TEM showed that continuous $500{\AA}$ thick buried oxide layer was formed with $300{\AA}$ thick top silicon layer in the sample. This study showed the possibility of SOI fabrication using the plasma source ion implantation with pulsed ICP source.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.176-182
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• 1992

t-Stress and junction leakage current characteristics of CVD-tungsten have been investigated. Stressversus continuous annealing temperature plot. shows hysteresis curve where the stress level of the cooling curveis higher than that of the heating curve. It is found that the thermal and intrinsic stress of tungsten film depositedby SiH4 reduction is higher than that by Hz reduction.The tungsten film deposited by SiHl reduction is in the tensile stress state below 700"Cnd the stress ofthe film decreses with increasing annealing temperature. The stress state changes into compressive stress atabout 700"Cnd the compressive stress increases rapidly with increasing temperature.Leakage current of the n+/p diode increases rapidly especially in the range of 400-450$^{\circ}$C with increasingdeposition temperature of the CVD-W by SiH4 reduction, which is due to the Si consumption by W encroachment.On the other hand leakage current of the n+/p diode slightly increases with increasing SiH4/WF6 ratio.h increasing SiH4/WF6 ratio.

• Korean Journal of Metals and Materials
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• v.46 no.6
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• pp.338-344
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• 2008

The crystallization kinetics of the $Cu_{43}Zr_{43}Al_7Be_7$ bulk metallic glass were studied by differential scanning calorimetry(DSC) in the continuous heating and isothermal annealing modes. Only one major peak could be detected on the DSC traces of $Cu_{43}Zr_{43}Al_7Be_7$ bulk amorphous alloy, and the activation energy for crystallization corresponding to the peak determined by the Kissinger method was resulted of 239 kJ/mol. The isothermal kinetic, analyzed by the Johnson-Mehl-Avrami equation yielded values for the Avrami exponents in the range 1.69 to 2.37, which implied a crystallization governed by a three-dimensioned growth. Primary phases were essentially the cubic structure CuZr together with the $Cu_{10}Zr_7$ phase. At higher temperature, the CuZr disappeared while the $Cu_{10}Zr_7$ became predominant. After long term annealing at 731 K, the phases were $Cu_{10}Zr_7$, $Cu_2ZrAl$ and $Al_3Zr_5$.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.229-229
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• 2010

With the scaling down of ultra large integrated circuits (ULSI) to the sub-50 nm technology node, the need for an ultra-thin, continuous and conformal diffusion barrier and Cu seed layer is increasing. However, diffusion barrier and Cu seed layer formation with a physical vapor deposition (PVD) method has become difficult as the technology node is reduced to 30 nm and beyond. Recent work on self-forming barrier processes using PVD Cu alloys have attracted great attention due to the capability of conformal ultra-thin barrier formation using a simple technique. However, as in the case of the conventional barrier and Cu seed layer, PVD of the Cu alloy seed layer will eventually encounter the difficulty in conformal deposition in narrow line trenches and via holes. Atomic layer deposition (ALD) has been known for its good step coverage and precise thickness control, and is a candidate technique for the formation of a thin conformal barrier layer and Cu seed layer. Conformal Cu-Mn seed layers were deposited by plasma enhanced atomic layer deposition (PEALD) at low temperature ($120^{\circ}C$), and the Mn content in the Cu-Mn alloys were controlled form 0 to approximately 10 atomic percent with various Mn precursor feeding times. Resistivity of the Cu-Mn alloy films decreased by annealing due to out-diffusion of Mn atoms. Out-diffused Mn atoms were segregated to the surface of the film and interface between a Cu-Mn alloy and $SiO_2$, resulting in self-formed $MnO_x$ and $MnSi_xO_y$, respectively. No inter-diffusion was observed between Cu and $SiO_2$ after annealing at $500^{\circ}C$ for 12 h, indicating an excellent diffusion barrier property of the $MnSi_xO_y$. The adhesion between Cu and $SiO_2$ was enhanced by the formation of $MnSi_xO_y$. Continuous and conductive Cu-Mn seed layers were deposited with PEALD into 32 nm $SiO_2$ trench, enabling a low temperature process, and the trench was perfectly filled using electrochemical plating (ECD) under conventional conditions. Thus, it is the resultant self-forming barrier process with PEALD Cu-Mn alloy film as a seed layer for plating Cu that has further potential to meet the requirement of the smaller than 30 nm node.

• Journal of Surface Science and Engineering
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• v.38 no.1
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• pp.7-13
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• 2005

Bismuth thin films were prepared on glass substrate with RF magnetron sputtering and effects of substrate temperature on surface morphology and their electrical transport properties were investigated. Grain growth of bismuth after nucleation and the onset of coalescense of grains at 393 K were observed with field emission secondary electron microscopy. Continuous thin films could not be obtained above 473 K because of grain segregation and island formation. Hall effect measurements showed that substrate heating yields the decrease of carrier density and the increase of mobility. Resistivity of bismuth film has its minimum (about 0.7 x 10/sup -3/ Ωcm) in range of 403～433 K. Annealing of bismuth films deposited at room temperature was carried out in a radiation furnace with flowing hydrogen gas. The change of resistivity was not significant due to cancellation of the decrease of carrier density and the increase of mobility. The abrupt change of electrical properties of film annealed above 523 K was found to be caused by partial oxidation of bismuth layer in x-ray diffraction analysis.

• Journal of the Korean Society of Propulsion Engineers
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• v.4 no.2
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• pp.46-53
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• 2000

Hot forging of aluminum alloy has the bad machinability due to continuous chip formation caused from the ductility The bad machinability requires a labor and a high cost to produce final products after hot forging. In industrial field, T4 heat treatment is performed to improve the machinability, and the annealing and the cold sizing are followed. In this study, a series of heat treatments are introduced during hot forging operation without T4 heat treatment after forming so that it improves the machinability with reduction of the number of operations and machining cost. Instead of T4 heat treatment, water cooling and air cooling are tried and compared to find out an optimum cooling condition

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.552-552
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• 2012

We fabricated reduced graphene oxide field-effect transistor (RGO-FET) on glass for highly sensitive temperature and IR detection. The device has the channels of RGO responsive to physical stimuli such as temperature and IR. The RGO sensing layers are fabricated from exfoliated graphene oxide sheets that are deposited to form a thin continuous network by electrostatic assembly. These graphene oxide networks are reduced toward reduce graphene oxide by exposure to a hydrazine hydrate vapor. To improve performance and eliminate interferences from oxygen and water vapor absorption to electrical properties of RGO-FET, the sensor devices were encapsulated by the tetratetracontane layer after annealing treatment. The device with encapsulation layer showed lower hysteresis, improved stability, and better repeatability. The temperature response of RGO-FET is examined by measuring changing the temperature, the device exhibited the high sensitivity and repeatability even with the temperature interval of 1 K. We also demonstrated that our devices have capability of IR sensing.