• Journal of Power Electronics
• /
• v.12 no.3
• /
• pp.377-386
• /
• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.1092-1095
• /
• 2001

Steady state thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin with a thickness of 25${\mu}$m. It was assumed that the generated heat which is mainly by the on-state voltage drop, 9V for 12kV diode, is dissipated by way of the conduction through diodes layers to bonding wire and of the convection at the surface of passivating resin. It was predicted by the thermal analysis that the temperature rise of a pn junction of the 12kV diode can reach at the range of 16∼34$^{\circ}C$ under the given boundary conditions. The thickness and thermal conductivity(0.3∼3W/m-K) of the passivating resin did little effect to lower thermal resistance of the diode. As the length of the bonding wire increased, which means the distance of heat conduction path became longer, the thermal resistance increased considerably. The thermal analysis results imply that the generated heat of the diode is dissipated mainly by the conduction through the route of diode-dummy wafer-bonding wire, which suggests to minimize the length of the wire for the lowest thermal resistance.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.5 no.4
• /
• pp.386-393
• /
• 2000

This paper presents an improved ZVS partial series resonant DC/DC converter (PSRC) with low conduction losses, suitable for high power and high frequency applications. The proposed PSRC have advantages of zero-voltage-switching (ZVS) of main switches for entire load ranges low conduction losses of main switches by decreasing current stresses. Also the reduction of the effective duty cycle is not occurred during the resonant period of the main circuit because the auxiliary circuit of the proposed converter is placed out of the main power path. The auxiliary circuit is composed with passive components, which are an inductor, two capacitors, two diodes, and a saturable inductor. An improved ZVS PSRC has so much characteristics with respect to the overall system efficiency and to the reduction of current stresses. The operation principles of the proposed converter are explained in detail and the various simulated and experimental results show the validity of the proposed converter.

• Korean Journal of Materials Research
• /
• v.11 no.7
• /
• pp.562-568
• /
• 2001

Devitrifiable solder glass/$ZrB_2$ sintered composites were prepared by using glass with the composition of $60ZnO-20B_2O_3-10SiO_2-10PbO$(in wt%) and $ZrB_2$, powder as starting materials under the $N_2$atmosphere. $ZrB_2$which the good conduction materials showed sensitive oxidation characteristics, because some parts of the $ZrB_2$in specimens changed into the insulated phase of $ZrO_2$. These Phenomena would be estimated that it caused a few amount of residual oxygen in the furnace and/or specimens and the coordination number change of $B_2O_3$ in the glass. The sintering temperature and the mixed ratios of each phase were control of large ranged the resistivity ranged from 10 to 10$^{3}{\Omega}/cm^2$ orders, and to make a conductible microstructure. From these results, it would be explained that the conduction path of $ZrB_2$particles built up within sintered glass matrix.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.41 no.5
• /
• pp.341-346
• /
• 2017

Knowing the mean free paths (MFPs) of thermal phonons is an essential step in performing heat transfer analysis for nanomaterials, and in determining the optimum design for tailoring the heat transfer characteristics of nanomaterials. In this study, we present a method that can be used to calculate accurately the phonon MFP spectra of nanostructures based on simple phonon kinetic theory. Here, the kinetic theory may be employed by extracting only the diffusive-transport part of the phonon spectrum (i.e., the MFPs are less than a thermal length). By considering phonon dispersion and polarization effects, the phonon MFP distributions of silicon at room temperature are calculated from phonon transport properties and the spectral MFP. Our results are validated by comparison with those of the first principle and MFP spectroscopy data.

• Proceedings of the KIEE Conference
• /
• 1995.07c
• /
• pp.1248-1251
• /
• 1995

This paper reports some results of an experimental investigation of planar double injection magnetic sensors. The threshold voltage proved to be very sensitive to an applied magnetic field. The magnitude and direction of the threshold voltage variation depends on the field strength and its orientation with respect to the conduction chennel. The positively-directed field pushes the carriers into the bulk causing an increase in the threhold voltage. These results seem to agree with a path modulation due to Lorentz force. The application of a negative field causes a negative variation, which is dependent on the surface recombination velocity of the silicon-$SiO_2$ interface.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.99.1-99.1
• /
• 2016

The materials for an electronic packaging provide diverse important functions including electrical contact to transfer signals from devices, isolation to protect from the environment and a path for heat conduction away from the devices. The packaging materials composed of metals, ceramics, polymers or combinations are crucial to the device operating properly and reliably. The demand of effective charge and heat transfer continuous to be challenge for the high-speed and high-power devices. Nanomaterials including graphene, carbon nanotube and boron nitride, have been designed for the purpose of exploiting the high thermal, electrical and mechanical properties by combining in the matrix of metal or polymer. In addition, considering the inherent electrical and surface properties of graphene, it is expected that graphene would be a good candidate for the surface layer of a template in the electroforming process. In this talk, I will present recent our on-going works in nanomaterials for microelectronic packaging: 1) porous graphene/Cu for heat dissipations, 2) carbon-metal composites for interconnects and 3) nanomaterials-epoxy composites as a thermal interface materials for electronic packaging.

• Carbon letters
• /
• v.2 no.3_4
• /
• pp.165-169
• /
• 2001

Modification of C/C composite bipolar plate for improving electrical conductivity was carried out by addition of electroconductive carbon black (EC-CB). Carbon black was carefully mixed to methanol-containing phenolic resin, impregnated into 2D-carbon fabrics, hot pressed and then carbonized to obtain composite plate. Inclusion of electro-conductive carbon black enhanced the electrical conductivity of the C/C composites by increasing the conduction path. Addition of 10 vol% carbon black increased the electrical conductivity from 5.5/${\Omega}cm$ to 32/${\Omega}cm$ and reduced the crack formation by filling effect, resulting in the increase of flexural properties of composite plate. However, at carbon black content over 10 vol%, flexural properties decreased by delaminating role of excess carbon black at the interface in C/C composites.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.4
• /
• pp.1552-1557
• /
• 2015

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.05a
• /
• pp.829-831
• /
• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 채널길이와 채널두께의 비에 따른 문턱전압 및 전도중심의 변화를 분석하고자한다. 비대칭 이중게이트 MOSFET는 상하단 게이트 전압에 의하여 전류흐름을 제어할 수 있어 단채널효과를 감소시킬 수 있다는 장점이 있다. 그러나 채널길이가 감소하면 필연적으로 발생하는 문턱전압의 급격한 변화는 소자 특성에 커다란 영향을 미치고 있다. 특히 상하단의 게이트 전압, 상하단의 게이트 산화막 두께 그리고 도핑분포변화에 따라 발생하는 전도중심의 변화는 문턱전압을 결정하는 중요 요소가 된다. 해석학적으로 문턱전압 및 전도중심을 분석하기 위하여 해석학적 전위분포를 포아송방정식을 통하여 유도하였다. 다양한 채널길이 및 채널두께에 대하여 전도중심과 문턱전압을 계산한 결과, 채널길이와 채널두께의 비 등 구조적 파라미터뿐만이 아니라 도핑분포 및 게이트 전압 등에 따라 전도중심과 문턱전압은 크게 변화한다는 것을 알 수 있었다.