• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.8
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• pp.4008-4022
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• 2016

This paper tries to extend the conventional conceptual framework of the Internet of Things (IoT) so as to reify an advanced pervasive IoT-community collaboration concept, which is called the process-aware Internet of Things. The extended conceptual framework is embodied as a referential architecture that can be a standardized reference model supporting the conceptual integration of the Internet of Things and the process awareness. The extended referential architecture covers the full range of the architectural details from abstracting the process-aware behavioral semantics to reifying the IoT-process enactments. These extended framework and architecture ought to be the theoretical basis for implementing a process-aware IoT-community computing system supporting process-aware collaborations of Things in pervasive computing environments. In particular, we do point up that the proposed framework of the process-aware Internet of Things is revised from the Internet of Things framework announced in ITU-T SG13³ Y.2060 [26] by integrating the novel concept of process awareness. We strongly believe that the extended conceptual framework and its referential architecture are able to deliver the novel and meaningful insight as a standardized platform for describing and achieving the goals of IoT-communities and societies.

• Journal of Information Technology and Architecture
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• v.11 no.2
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• pp.225-233
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• 2014

In this paper an architecture for 3D audio core algorithm evaluation database system. Due to increase of 3D audio system through multimedia device, an evaluation system is required for evaluating the 3D core algorithms for developing 3D audio system. Conventional evaluation systems have some problems. Researchers have to learn usage of evaluation system, in addition it is inefficient to use and search audio sources because audio sources are not indexed in general. To solve these problems, we design the architecture of 3D audio core algorithm evaluation database system enabling to automatically evaluate core algorithms using database management system. Also we define XML metadata scheme for information of saved audio source in database. This approach allows improving efficiency of search audio source and use of audio database.

• Journal of Information Processing Systems
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• v.18 no.2
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• pp.188-196
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• 2022

Recently, neural architecture search (NAS) has received increasing attention as it can replace human experts in designing the architecture of neural networks for different tasks and has achieved remarkable results in many challenging tasks. In this study, a path-based computation neural architecture encoder (PCE) was proposed. Our PCE first encodes the computation of information on each path in a neural network, and then aggregates the encodings on all paths together through an attention mechanism, simulating the process of information computation along paths in a neural network and encoding the computation on the neural network instead of the structure of the graph, which is more consistent with the computational properties of neural networks. We performed an extensive comparison with eight encoding methods on two commonly used NAS search spaces (NAS-Bench-101 and NAS-Bench-201), which included a comparison of the predictive capabilities of performance predictors and search capabilities based on two search strategies (reinforcement learning-based and Bayesian optimization-based) when equipped with different encoders. Experimental evaluation shows that PCE is an efficient encoding method that effectively ranks and predicts neural architecture performance, thereby improving the search efficiency of neural architectures.

• International Journal of Computer Science & Network Security
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• v.24 no.5
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• pp.191-197
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• 2024

Software reuse gives the meaning for rapid software development and the quality of the software. Most of the Java components/libraries open-source are available only in Java Archive (JAR) file format. When a software design enters into the development process, the developer needs to select necessary JAR files manually via analyzing the given software architecture and related JAR files. This paper proposes an automated approach, JarBot, to suggest all the necessary JAR files for given software architecture in the development process. All related JAR files will be downloaded from the internet based on the extracted information from the given software architecture (class diagram). Class names, method names, and attribute names will be extracted from the downloaded JAR files and matched with the information extracted from the given software architecture to identify the most relevant JAR files. For the result and evaluation of the proposed system, 05 software design was developed for 05 well-completed software project from GitHub. The proposed system suggested more than 95% of the JAR files among expected JAR files for the given 05 software design. The result indicated that the proposed system is suggesting almost all the necessary JAR files.

• ETRI Journal
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• v.32 no.2
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• pp.330-332
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• 2010

We propose a new matched filter architecture for chirp spread spectrum in IEEE 802.15.4a. By using relations among the four subchirps, the proposed architecture comprises four subfilters utilizing only a set of coefficients matched to the first subchirp. The four subfilters share adders and registers, and as a result, the required adders and registers for implementation are reduced.

• Journal of Computing Science and Engineering
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• v.8 no.4
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• pp.215-227
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• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.31-34
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• 2005

Mobile devices, such as PDAs, portable multimedia players, are more likely to encompass large storage devices with prevalance of high-quality multimedia contents. This paper proposes an object-based multimedia contents storage architecture that employs the object-based storage device model and the iSCSI protocol. It also provides a multimedia content player that operates directly with the proposed storage architecture. We implement both the proposed storage architecture and the multimedia content player upon the Linux environment. Performance evaluation by playing MP3 multimedia contents reveals that the proposed storage architecture reduces the total power consumption by 9%, compared with an existing networked storage. This enhancement is mainly contributed to the fact that a large portion of the file system is moved into the object-based multimedia contents storage from the mobile device.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11b
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• pp.361-363
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• 2005

EPC Network Architecture는 일반적으로 RFID 미들웨어 시스템의 표준안으로 응용되고 있다. RFID 미들웨어 시스템은 그 사용에 있어 서브시스템들의 장애 발생이 예상되지만 이를 탐지하고 복구하는 가용성(Availability)에 대한 지원은 부족하다. 따라서 본 논문은 EPC Network Architecture를 응용한 미들웨어 시스템을 개발함에 있어 가용성을 보장하는 방안을 제시한다. 그리고 가용성의 특성 가운데 장애 복구 기법에 더욱 초점을 두고 일반적인 수준의 가용성 또는 높은 수준의 가용성을 제공하는 다양한 기법들을 제시한다.

• International Journal of Computer Science & Network Security
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• v.23 no.9
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• pp.100-110
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• 2023

The Internet of Things (IoT) is the most creative and focused technology to be employed today. It increases the living conditions of both individuals and society. IoT offers the ability to recognize and incorporate physical devices across the globe through a single network by connecting different devices by using various technologies. As part of IoTs, significant questions are posed about access to computer and user privacy-related personal details. This article demonstrates the three-layer architecture composed of the sensor, routing, and implementation layer, respectively, by highlighting the security risks that can occur in various layers of an IoT architecture. The article also involves countermeasures and a convenient comparative analysis by discussing major attacks spanning from detectors to application. Furthermore, it deals with the basic protocols needed for IoT to establish a reliable connection between objects and items.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design