• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.10C
• /
• pp.1000-1010
• /
• 2006

This paper proposes a new architecture for DCT-based motion estimation and compensation. Previous methods do riot take sufficient advantage of the sparseness of 2-D DCT coefficients to reduce execution time. We first derive a recursion equation to perform DCT domain motion estimation more efficiently; we then use it to develop a wavefront array processor (WAP) consisting of processing elements. In addition, we show that the recursion equation enables motion predicted images with different frequency bands, for example, from the images with low frequency components to the images with low and high frequency components. The wavefront way Processor can reconfigure to different motion estimation algorithms, such as logarithmic search and three step search, without architectural modifications. These properties can be effectively used to reduce the energy required for video encoding and decoding. The proposed WAP architecture achieves a significant reduction in computational complexity and processing time. It is also shown that the motion estimation algorithm in the transform domain using SAD (Sum of Absolute Differences) matching criterion maximizes PSNR and the compression ratio for the practical video coding applications when compared to tile motion estimation algorithm in the spatial domain using either SAD or SSD.

• Journal of the Korea Safety Management & Science
• /
• v.18 no.3
• /
• pp.127-135
• /
• 2016

Korean automobile industrial is in a difficult situation because of more competitive global market and lower demand. Therefore, domestic as well as global automobile manufacturers are making greater efforts in cost reduction to strengthen the competitiveness. According to statistical data, logistics cost in domestic manufacturers is higher than advanced countries. In this study, we developed program to effectively manage standard time of procurement logistics, and confirm based on A-automobile factory data. For the purpose, we develop the system which is possible to manage standard time as well as calculate man-hour. Program is not just for calculating and managing standard man-hour, scenarios analysis function will be added to calculate benefit while introduce logistics automated equipment. In this study we propose scenario using AGV instead of electric motor while move component. In the scenario analysis, job constitution is changed, and then we use system to compare the result. We can confirm standard man-hour is reduced from 22.3M/H to 14.3M/H. In future research, it is necessary scenario analysis function, and develop algorithm with realistic constraint condition.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.22 no.6
• /
• pp.173-178
• /
• 2022

Recently, a recommendation system using deep learning in social network services has been actively studied. However, in the case of a recommendation system using deep learning, the cold start problem and the increased learning time due to the complex computation exist as the disadvantage. In this paper, the user-tailored exercise routine recommendation algorithm is proposed using the user's metadata. Metadata (the user's height, weight, sex, etc.) set as the input of the model is applied to the designed model in the proposed algorithms. The exercise recommendation system model proposed in this paper is designed based on the neural collaborative filtering (NCF) algorithm using multi-layer perceptron and matrix factorization algorithm. The learning proceeds with proposed model by receiving user metadata and exercise information. The model where learning is completed provides recommendation score to the user when a specific exercise is set as the input of the model. As a result of the experiment, the proposed exercise recommendation system model showed 10% improvement in recommended performance and 50% reduction in learning time compared to the existing NCF model.

• The KIPS Transactions:PartA
• /
• v.16A no.6
• /
• pp.419-426
• /
• 2009

To realistically simulate fluid, the Navier-Stokes equations are generally used. Solving these Navier-Stokes equations on the Eulerian framework, the non-linear advection terms invoke heavy computation and thus Semi-Lagrangian methods are used as an approximated way of solving them. In the Semi-Lagrangian methods, the locations of advection sources are traced and the physical values at the traced locations are interpolated. In the case of Stam's method, there are relatively many chances of numerical losses, and thus there have been efforts to correct these numerical errors. In most cases, they have focused on the numerical interpolation processes, even simultaneously using particle-based methods. In this paper, we propose a new approach to reduce the numerical losses, through improving the tracing method during the advection calculations, without any modifications on the Eulerian framework itself. In our method, we trace the grids with the velocities which will let themselves to be moved to the current target position, differently from the previous approaches, where velocities of the current target positions are used. From the intuitive point of view, we adopted the simple physical observation: the physical quantities at a specific position will be moved to the new location due to the current velocity. Our method shows reasonable reduction on the numerical losses during the smoke simulations, finally to achieve real-time processing even with enhanced realities.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.271-274
• /
• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• The Journal of the Acoustical Society of Korea
• /
• v.14 no.1E
• /
• pp.22-29
• /
• 1995

Code excited Linear Prediction(CELP) vocoder exhibits good performance at data rates below 4.8 kbps. The major drawback of CELP type coders is their large amount of computation. In this paper, we propose a new pitch searching method that preseves the quality of the CELP vodocer reducing computational complexity. The basic idea is that pregrasps preliminary pitches about signal and performs pitch search only about the preliminary pitches. Applying the proposed method to the CELP vocoder, we can reduce complexity about 90% in th pitch search.

• International journal of advanced smart convergence
• /
• v.8 no.4
• /
• pp.194-199
• /
• 2019

As the performance of the system increases, more parallelized data is being processed than single processing of data. Today's cpu structure has been developed to leverage multicore, and hence data processing methods are being developed to enable parallel processing. In recent years desktop cpu has increased multicore, data is growing exponentially, and there is also a growing need for data processing as artificial intelligence develops. This neural network of artificial intelligence consists of a matrix, making it advantageous for parallel processing. This paper aims to speed up the processing of the system by using raspberrypi to implement the cluster building and parallel processing system against the backdrop of the foregoing discussion. Raspberrypi is a credit card-sized single computer made by the raspberrypi Foundation in England, developed for education in schools and developing countries. It is cheap and easy to get the information you need because many people use it. Distributed processing systems should be supported by programs that connected multiple computers in parallel and operate on a built-in system. RaspberryPi is connected to switchhub, each connected raspberrypi communicates using the internal network, and internally implements parallel processing using the Message Passing Interface (MPI). Parallel processing programs can be programmed in python and can also use C or Fortran. The system was tested for parallel processing as a result of multiplying the two-dimensional arrangement of 10000 size by 0.1. Tests have shown a reduction in computational time and that parallelism can be reduced to the maximum number of cores in the system. The systems in this paper are manufactured on a Linux-based single computer and are thought to require testing on systems in different environments.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.10 no.6
• /
• pp.2851-2873
• /
• 2016

Cloud storage as a service provides high scalability and availability as per need of user, without large investment on infrastructure. However, data security risks, such as confidentiality, privacy, and integrity of the outsourced data are associated with the cloud-computing model. Over the year's techniques such as, remote data checking (RDC), data integrity protection (DIP), provable data possession (PDP), proof of storage (POS), and proof of retrievability (POR) have been devised to frequently and securely check the integrity of outsourced data. In this paper, we improve the efficiency of PDP scheme, in terms of computation, storage, and communication cost for large data archives. By utilizing the capabilities of JAR and ZIP technology, the cost of searching the metadata in proof generation process is reduced from O(n) to O(1). Moreover, due to direct access to metadata, disk I/O cost is reduced and resulting in 50 to 60 time faster proof generation for large datasets. Furthermore, our proposed scheme achieved 50% reduction in storage size of data and respective metadata that result in providing storage and communication efficiency.

• The KIPS Transactions:PartB
• /
• v.9B no.3
• /
• pp.369-374
• /
• 2002

In this paper, we propose the react-time car license plate recognition algorithm using intensity variation and geometric pattern vector. Generally, difference of car license plate region between character and background is more noticeable than other regions. And also, car license plate region usually shows high density values as well as constant intensity variations. Based on these characteristics, we first extract car license plate region using intensity variations. Secondly, lightness compensation process is performed on the considerably dark and brightness input images to acquire constant extraction efficiency. In the proposed recognition step, we first pre-process noise reduction and thinning steps. And also, we use geometric pattern vector to extract features which independent on the size, translation, and rotation of input values. In the experimental results, the proposed method shows better computation times than conventional circular pattern vector and better extraction results regardless of irregular environment lighting conditions as well as noise, size, and location of plate.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.6
• /
• pp.42-49
• /
• 2000

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.