• 제목/요약/키워드: computation complexity

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QRD-LS Adaptive Algorithm with Efficient Computational Complexity (효율적 계산량을 가지는 QRD-LS 적응 알고리즘)

  • Cho, Hae-Seong;Cho, Ju-Phil
    • Journal of Satellite, Information and Communications
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    • v.5 no.1
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    • pp.85-89
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    • 2010
  • This paper proposes a new QRD-LS adaptive algorithm with computational complexity of O(N). The main idea of proposed algorithm(D-QR-RLS) is based on the fact that the computation for the unit vector of is made from the process during Givens Rotation. The performance of the algorithm is evaluated through computer simulation of FIR system identification problem. As verified by simulation results, this algorithm exhibits a good performance. And, we can see the proposed algorithm converges to optimal coefficient vector theoretically.

An Analysis on the Echo Cancellation Algorithm Reducing the Computational Quantities

  • Lee, Haeng-Woo
    • Journal of information and communication convergence engineering
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    • v.2 no.2
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    • pp.89-92
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    • 2004
  • An adaptive algorithm for reducing the hardware complexity is presented. This paper proposes a modified LMS algorithm for the adaptive system and analyzes its convergence characteristics mathematically. An objective of the proposed algorithm is to reduce the hardware complexity. In order to test the performances, it is applied to the echo canceller, and a program is described. The results from simulations show that the echo canceller adopting the proposed algorithm achieves almost the same performances as one adopting the NLMS algorithm. If an echo canceller is implemented with this algorithm, its computation quantities are reduced to the one third as many as the one that is implemented with the NLMS algorithm, without so much degradation of performances.

On a Reduction of Pitch Searching Time by Preliminary Pitch in the CELP Vocoder

  • Bae, Seong-Gyun;Kim, Hyung-Rae;Kim, Dae-Sik;Bae, Myung-Jin
    • Proceedings of the Acoustical Society of Korea Conference
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    • 1994.06a
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    • pp.1104-1111
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    • 1994
  • Code Excited Linear Prediction(CELP) as a speech coder exhibits good performance at data rates below 4.8 kbps. The major drawback to CELP type coders is their large amount of computation. In this paper, we propose a new pitch search method that preserves the quality of the CELP vocoder with reduced complexity. The basic idea is to restrict the pitch searching range by estimating the preliminary pitches. Applying the proposed method to the CELP vocoder, we can get approximately 87% complexity reduction in the pitch search.

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ON A REDUCTION OF PITCH SEARCHING TIME BY PREPROCESSING IN THE CELP VOCODER

  • Kim, Daesik;Bae, Myungjin;Kim, Jongjae;Byun, Kyungjin;Han, Kichun;Yoo, Hahyoung
    • Proceedings of the Acoustical Society of Korea Conference
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    • 1994.06a
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    • pp.904-911
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    • 1994
  • Code Excited Linear Prediction (CELP) speech coders exhibit good performance at data rates below 4.8 kbps. The major drawback to CELP type coders is their many computation. In this paper, we propose a new pitch search method that preserves the quality of the CELP vocoder with reducing complexity. The basic idea is to apply the preprocessing technique beforehand grasping the autocorrelation property of speech waveform. By using the proposed method, we can get approximately 77% complexity reduction in the pitch search.

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Performance Analysis of DNN inference using OpenCV Built in CPU and GPU Functions (OpenCV 내장 CPU 및 GPU 함수를 이용한 DNN 추론 시간 복잡도 분석)

  • Park, Chun-Su
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.1
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    • pp.75-78
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    • 2022
  • Deep Neural Networks (DNN) has become an essential data processing architecture for the implementation of multiple computer vision tasks. Recently, DNN-based algorithms achieve much higher recognition accuracy than traditional algorithms based on shallow learning. However, training and inference DNNs require huge computational capabilities than daily usage purposes of computers. Moreover, with increased size and depth of DNNs, CPUs may be unsatisfactory since they use serial processing by default. GPUs are the solution that come up with greater speed compared to CPUs because of their Parallel Processing/Computation nature. In this paper, we analyze the inference time complexity of DNNs using well-known computer vision library, OpenCV. We measure and analyze inference time complexity for three cases, CPU, GPU-Float32, and GPU-Float16.

Diffusive DTW Algorithm for Optimizing Distance Matrix Computation Structure (거리 행렬 연산 구조 최적화를 위한 확산 동적 시간 왜곡(Diffusive DTW) 알고리즘)

  • Kim, Young-tak;Jin, Kyo-hong
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2022.10a
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    • pp.93-96
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    • 2022
  • DTW can eliminate gaps between sequences of different lengths and find out the similarity of patterns, but due to the time and space complexity, it requires a high computational cost on large datasets. In this paper, we propose a DDTW algorithm that not only reduces computational costs but also has no error in the results. In addition, the algorithm complexity of DTW and DDTW is compared by measuring the computational time according to the length of the sequence. Simulation results show a noticeable reduction in computational time in DDTW compared to DTW.

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High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture

  • Park, Jeong-In;Lee, Ki-Hoon;Choi, Chang-Seok;Lee, Han-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.3
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    • pp.193-202
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    • 2010
  • This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

Design of Low Complexity Human Anxiety Classification Model based on Machine Learning (기계학습 기반 저 복잡도 긴장 상태 분류 모델)

  • Hong, Eunjae;Park, Hyunggon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.9
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    • pp.1402-1408
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    • 2017
  • Recently, services for personal biometric data analysis based on real-time monitoring systems has been increasing and many of them have focused on recognition of emotions. In this paper, we propose a classification model to classify anxiety emotion using biometric data actually collected from people. We propose to deploy the support vector machine to build a classification model. In order to improve the classification accuracy, we propose two data pre-processing procedures, which are normalization and data deletion. The proposed algorithms are actually implemented based on Real-time Traffic Flow Measurement structure, which consists of data collection module, data preprocessing module, and creating classification model module. Our experiment results show that the proposed classification model can infers anxiety emotions of people with the accuracy of 65.18%. Moreover, the proposed model with the proposed pre-processing techniques shows the improved accuracy, which is 78.77%. Therefore, we can conclude that the proposed classification model based on the pre-processing process can improve the classification accuracy with lower computation complexity.

A Study on Multiple Bitrate Output Video Transcoder based on Requantiation and Recoding processing by Sharing (재양자화 및 재부호화 처리 공유에 의한 멀티레이트 출력 비디오 트랜스코더 검토)

  • Song, Dae-Geon
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.4 no.1
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    • pp.9-16
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    • 2011
  • In this paper, we propose an efficience transcoder architecture to support a simutaneous multibitrate output. First, we discuss about some architectures to realize this feature. Next, we explain the proposed architecture, it shares not only VLD-IQ but alse Q-VlD which have the same quantization step sizes each other. We anlyze the numbers of Q-VLC times per on Macroblock to the investigate an effect of sharing, and evaluate its computation complexity. The result of simulation, that complexity has an upper limit and it cn support any numbers of bitstream by about 3~6 times complexity than single output.

An Efficient Mode Decision Method for Fast Intra Prediction of SVC (SVC에서 빠른 인트라 예측을 위한 효율적인 모드 결정 방법)

  • Cho, Mi-Sook;Kang, Jin-Mi;Chung, Ki-Dong
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.4
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    • pp.280-283
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    • 2009
  • To improve coding performance of scalable video coding which is an emerging video coding standard as an extension of H.264/AVC, SVC uses not only intra prediction and inter prediction but inter-layer prediction. This causes a problem that computational complexity is increased. In this paper, we propose an efficient intra prediction mode decision method in spatial enhancement layer to reduce the computational complexity. The proposed method selects Inra_BL mode using RD cost of Intra_BL in advance. After that, intra mode is decided by only comparing DC modes. Experimental results show that the proposed method reduces 59% of the computation complexity of intra prediction coding, while the degradation in video quality is negligible.