• 제목/요약/키워드: computation and communication efficiency

검색결과 112건 처리시간 0.029초

평판압연공정 유한요소해석의 분산병렬처리에 관한 연구 (Finite element analysis of strip rolling process using distributive parallel algorithm)

  • 권기찬;윤성기
    • 대한기계학회논문집A
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    • 제21권12호
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    • pp.2096-2105
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    • 1997
  • A parallel approach using a network of engineering workstations is presented for the efficient computation in the elastoplastic analysis of strip rolling process. The domain decomposition method coupled with the frontal solver for elimination of internal degrees of freedom in each subdomain is used. PVM is used for message passing and synchronization between processors. A 2-D plane strain problem and the strip rolling process are analyzed to demonstrate the performance of the algorithm and factors that have a great effect on efficiency are discussed. In spite of much communication time on the network the result illustrates the advantages of this parallel algorithm over its corresponding sequential algorithm.

A Certificateless-based One-Round Authenticated Group Key Agreement Protocol to Prevent Impersonation Attacks

  • Ren, Huimin;Kim, Suhyun;Seo, Daehee;Lee, Imyeong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제16권5호
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    • pp.1687-1707
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    • 2022
  • With the development of multiuser online meetings, more group-oriented technologies and applications for instance collaborative work are becoming increasingly important. Authenticated Group Key Agreement (AGKA) schemes provide a shared group key for users with after their identities are confirmed to guarantee the confidentiality and integrity of group communications. On the basis of the Public Key Cryptography (PKC) system used, AGKA can be classified as Public Key Infrastructure-based, Identity-based, and Certificateless. Because the latter type can solve the certificate management overhead and the key escrow problems of the first two types, Certificateless-AGKA (CL-AGKA) protocols have become a popular area of research. However, most CL-AGKA protocols are vulnerable to Public Key Replacement Attacks (PKRA) due to the lack of public key authentication. In the present work, we present a CL-AGKA scheme that can resist PKRA in order to solve impersonation attacks caused by those attacks. Beyond security, improving scheme efficiency is another direction for AGKA research. To reduce the communication and computation cost, we present a scheme with only one round of information interaction and construct a CL-AGKA scheme replacing the bilinear pairing with elliptic curve cryptography. Therefore, our scheme has good applicability to communication environments with limited bandwidth and computing capabilities.

피더부하 균등화지수를 이용한 배전계통의 긴급정전복구 및 부하균등화 (Emergency Service Restoration and Load Balancing in Distribution Networks Using Feeder Loadings Balance Index)

  • 최상열;정호성;신명철
    • 대한전기학회논문지:전력기술부문A
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    • 제51권5호
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    • pp.217-224
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    • 2002
  • This paper presents an algorithm to obtain an approximate optimal solution for the service restoration and load balancing of large scale radial distribution system in a real-time operation environment. Since the problem is formulated as a combinatorial optimization problem, it is difficult to solve a large-scale combinatorial optimization problem accurately within the reasonable computation time. Therefore, in order to find an approximate optimal solution quickly, the authors proposed an algorithm which combines optimization technique called cyclic best-first search with heuristic based feeder loadings balance index for computational efficiency and robust performance. To demonstrate the validity of the proposed algorithm, numerical calculations are carried out the KEPCO's 108 bus distribution system.

Blind Neural Equalizer using Higher-Order Statistics

  • Lee, Jung-Sik
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • 제2권3호
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    • pp.174-178
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    • 2002
  • This paper discusses a blind equalization technique for FIR channel system, that might be minimum phase or not, in digital communication. The proposed techniques consist of two parts. One is to estimate the original channel coefficients based on fourth-order cumulants of the channel output, the other is to employ RBF neural network to model an inverse system fur the original channel. Here, the estimated channel is used as a reference system to train the RBF. The proposed RBF equalizer provides fast and easy teaming, due to the structural efficiency and excellent recognition-capability of R3F neural network. Throughout the simulation studies, it was found that the proposed blind RBF equalizer performed favorably better than the blind MLP equalizer, while requiring the relatively smaller computation steps in tranining.

안전하고 효율적인 동적 멀티캐스트 키 관리 구조 제안 (A Proposal of Secure and Efficient Dynamic Multicast Key Management Structure)

  • 박희운;이임영
    • 한국멀티미디어학회논문지
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    • 제4권2호
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    • pp.145-160
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    • 2001
  • 통신 및 컴퓨터의 보급 발전을 통해 공개 네트워크 상에서 그룹에 기반한 통신 응용 서비스의 요구가 증가하고 있다. 이러한 필요성에 따라 멀티캐스트 기반 구조에 대한 연구가 활발히 진행되고 있다. 하지만 멀티캐스트 구조에 대한 안전성과 효율성 및 확장성 부분에 대한 해결책은 아직 미비한 상태이다. 본 연구에서는 기존의 대표적인 멀티캐스트 키 관리 구조를 고찰함과 동시에 안전성과 효율성 및 확장성을 분식한다. 이에 기초해 확장성을 제공하는 안전하고 효율적인 멀티캐스트 키 관리 구조를 제안하고, 기존 방식과 통신 및 계산량 부분에 비교 분석을 통해 그 효율성을 확인한다.

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Energy Efficient Architecture Using Hardware Acceleration for Software Defined Radio Components

  • Liu, Chen;Granados, Omar;Duarte, Rolando;Andrian, Jean
    • Journal of Information Processing Systems
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    • 제8권1호
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    • pp.133-144
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    • 2012
  • In order to make cognitive radio systems a practical technology to be deployed in real-world scenarios, the core Software Defined Radio (SDR) systems must meet the stringent requirements of the target application, especially in terms of performance and energy consumption for mobile platforms. In this paper we present a feasibility study of hardware acceleration as an energy-efficient implementation for SDR. We identified the amplifier function from the Software Communication Architecture (SCA) for hardware acceleration since it is one of the functions called for most frequently and it requires intensive floating-point computation. Then, we used the Virtex5 Field-Programmable Gate Array (FPGA) to perform a comparison between compiler floating-point support and the on-chip floating-point support. By enabling the on-chip floating-point unit (FPU), we obtained as high as a 2X speedup and 50% of the overall energy reduction. We achieved this with an increase of the power consumption by no more than 0.68%. This demonstrates the feasibility of the proposed approach.

Efficient Continuous Skyline Query Processing Scheme over Large Dynamic Data Sets

  • Li, He;Yoo, Jaesoo
    • ETRI Journal
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    • 제38권6호
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    • pp.1197-1206
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    • 2016
  • Performing continuous skyline queries of dynamic data sets is now more challenging as the sizes of data sets increase and as they become more volatile due to the increase in dynamic updates. Although previous work proposed support for such queries, their efficiency was restricted to small data sets or uniformly distributed data sets. In a production database with many concurrent queries, the execution of continuous skyline queries impacts query performance due to update requirements to acquire exclusive locks, possibly blocking other query threads. Thus, the computational costs increase. In order to minimize computational requirements, we propose a method based on a multi-layer grid structure. First, relational data object, elements of an initial data set, are processed to obtain the corresponding multi-layer grid structure and the skyline influence regions over the data. Then, the dynamic data are processed only when they are identified within the skyline influence regions. Therefore, a large amount of computation can be pruned by adopting the proposed multi-layer grid structure. Using a variety of datasets, the performance evaluation confirms the efficiency of the proposed method.

A Scalable Data Integrity Mechanism Based on Provable Data Possession and JARs

  • Zafar, Faheem;Khan, Abid;Ahmed, Mansoor;Khan, Majid Iqbal;Jabeen, Farhana;Hamid, Zara;Ahmed, Naveed;Bashir, Faisal
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제10권6호
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    • pp.2851-2873
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    • 2016
  • Cloud storage as a service provides high scalability and availability as per need of user, without large investment on infrastructure. However, data security risks, such as confidentiality, privacy, and integrity of the outsourced data are associated with the cloud-computing model. Over the year's techniques such as, remote data checking (RDC), data integrity protection (DIP), provable data possession (PDP), proof of storage (POS), and proof of retrievability (POR) have been devised to frequently and securely check the integrity of outsourced data. In this paper, we improve the efficiency of PDP scheme, in terms of computation, storage, and communication cost for large data archives. By utilizing the capabilities of JAR and ZIP technology, the cost of searching the metadata in proof generation process is reduced from O(n) to O(1). Moreover, due to direct access to metadata, disk I/O cost is reduced and resulting in 50 to 60 time faster proof generation for large datasets. Furthermore, our proposed scheme achieved 50% reduction in storage size of data and respective metadata that result in providing storage and communication efficiency.

OpenCL 및 Embedded GPU를 이용한 영상 특징 추출 및 파노라마 영상 생성의 병렬화 (Parallelization of Feature Detection and Panorama Image Generation using OpenCL and Embedded GPU)

  • 강승헌;이승재;이만희;박인규
    • 방송공학회논문지
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    • 제19권3호
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    • pp.316-328
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    • 2014
  • 본 논문에서는 최신 embedded GPU를 사용하여 영상의 특징 추출 알고리즘(SIFT, SURF)을 병렬화하고, 특징 추출 및 정합 결과를 이용하여 파노라마 영상을 GPU에서 고속으로 생성하는 방법을 제안한다. 병렬화 된 알고리즘의 GPGPU(general purpose computation on GPU) 구현은 최신 스마트폰의 embedded GPU에서 지원하기 시작한 OpenCL을 이용하였다. 본 논문에서는 GPU에서 OpenGL Shading Language(GLSL)를 이용한 기존의 병렬화와 OpenCL을 이용한 새로운 병렬화 구현 결과를 효과적인 코드 구현 방법과 수행속도 관점에서 비교하였다. 실험결과, OpenCL은 GLSL과 유사한 수행 속도를 보였으며 embedded CPU와 비교하여 약 3~4배 빠른 수행속도를 보였다. 구현한 특징 추출 결과의 응용 사례로써, 특징 정합을 통한 영상 정합을 GPU상에서 병렬 수행하여 여러 장의 영상으로부터 파노라마 영상을 고속으로 생성하는 사례를 보인다.

효율적인 다중 채널 On-Chip-Bus를 위한 SoC Network Architecture (SoC Network Architecture for Efficient Multi-Channel On-Chip-Bus)

  • 이상헌;이찬호;이혁재
    • 대한전자공학회논문지SD
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    • 제42권2호
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    • pp.65-72
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    • 2005
  • 공정기술과 EDA 툴의 발전에 따라서 하나의 실리콘 다이(Die)에 많은 IP가 집적되고 멀티프로세서가 포함되는 SoC 구조가 가능해지고 있다 그러나 대부분의 기존 SoC 버스는 공유버스 구조라는 문제점으로 인해 통신의 병목현상이 발생하고 이는 전체 시스템 성능을 저하시키는 요인이 된다. 많은 경우에 멀티프로세서 시스템의 성능은 CPU 자체의 속도보다는 효율적인 통신과 균형있는 연산의 분배가 좌우하게 된다 따라서 충분한 SoC 버스 대역폭(Bandwidth)을 확보하기 위한 하나의 해결책으로 크로스바 라우터(Crossbar Router)를 이용하여 효율적인 온 칩 버스구조인 SoC Network Architecture(SNA)를 제안한다. 제안된 SNA구조는 다중 마스터(multi-master)에 대해 다중 채널(multi-channel)을 제공하여 통신의 병목현상을 크게 줄일 수 있으며 뛰어난 확장성을 지원한다. 제안된 구조에 따라 모델 시스템을 설계하고 시뮬레이션을 진행한 결과 AMBA AHB 버스에 비해 평균 $40\%$ 이상 효율이 증가했다.