• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.463-463
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• 2012

ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.334-334
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• 2012

Transparent oxide semiconductors have recently attracted much attention as channel layer materials due to advantageous electrical and optical characteristics such as high mobility, high stability, and good transparency. In addition, transparent oxide semiconductor can be fabricated at low temperature with a low production cost and it permits highly uniform devices such as large area displays. A variety of thin film transistors (TFTs) have been studied including ZnO, InZnO, and InGaZnO as the channel layer. Recently, there are many studies for substitution of Ga in InGaZnO TFTs due to their problem, such as stability of devices. In this work, new quaternary compound materials, tantalum-indium-tin oxide (TaInSnO) thin films were fabricated by using co-sputtering and used for the active channel layer in thin film transistors (TFTs). We deposited TaInSnO films in a mixed gas (O2+Ar) atmosphere by co-sputtering from Ta and ITO targets, respectively. The electric characteristics of TaInSnO TFTs and thin films were investigated according to the RF power applied to the $Ta_2O_5$ target. The addition of Ta elements could suppress the formation of oxygen vacancies because of the stronger oxidation tendency of Ta relative to that of In or Sn. Therefore the free carrier density decreased with increasing RF power of $Ta_2O_5$ in TaInSnO thin film. The optimized characteristics of TaInSnO TFT showed an on/off current ratio of $1.4{\times}108$, a threshold voltage of 2.91 V, a field-effect mobility of 2.37 cm2/Vs, and a subthreshold swing of 0.48 V/dec.

• Transactions on Electrical and Electronic Materials
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• 제11권2호
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• pp.73-76
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• 2010

The copper indium disulfide ($CuInS_2$) thin film was manufactured using sputtering and thermal evaporation methods, and the annealing with sulfurization process was used in the vacuum chamber to the substrate temperature on the glass substrate, the annealing temperature and the composition ratio, and the characteristics thereof were investigated. The $CuInS_2$ thin film was manufactured by the sulfurization of a soda lime glass (SLG) Cu/In/S stacked [1] elemental layer deposited on a glass substrate by vacuum chamber annealing [2] with sulfurization for various times at a temperature of substrate temperature of $200^{\circ}C$. The structure and electrical properties of the film was measured in order to determine the optimum conditions for the growth of $CuInS_2$ ternary compound semiconductor $CuInS_2$ thin films with a non-stoichiometric composition. The physical properties of the thin film were investigated under various fabrication conditions [3,4], including the substrate temperature, annealing temperature and annealing time by X-ray diffraction (XRD), field Emission scanning electron microscope (FE-SEM), and Hall measurement systems. [5] The sputtering rate depending upon the DC/RF power was controlled so that the composition ratio of Cu versus In might be around 1:1, and the substrate temperature affecting the quality of the film was varied in the range of room temperature (RT) to $300^{\circ}C$ at intervals of $100^{\circ}C$, and the annealing temperature of the thin film was varied RT to $550^{\circ}C$ in intervals of $100^{\circ}C$.

• 한국재료학회지
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• 제24권8호
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• pp.434-442
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• 2014

Serious environmental problems have been caused by the greenhouse effect due to carbon dioxide($CO_2$) or nitrogen oxides($NO_x$) generated by the use of fossil fuels, including oil and liquefied natural gas. Many countries, including our own, the United States, those of the European Union and other developed countries around the world; have shown growing interest in clean energy, and have been concentrating on the development of new energy-saving materials and devices. Typical non-fossil-fuel sources include solar cells, wind power, tidal power, nuclear power, and fuel cells. In particular, organic solar cells(OSCs) have relatively low power-conversion efficiency(PCE) in comparison with inorganic(silicon) based solar cells, compound semiconductor solar cells and the CIGS [$Cu(In_{1-x}Ga_x)Se_2$] thin film solar cells. Recently, organic cell efficiencies greater than 10 % have been obtained by means of the development of new organic semiconducting materials, which feature improvements in crystalline properties, as well as in the quantum-dot nano-structure of the active layers. In this paper, a brief overview of solar cells in general is presented. In particular, the current development status of the next-generation OSCs including their operation principle, device-manufacturing processes, and improvements in the PCE are described.

• 한국전자파학회논문지
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• 제23권11호
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• pp.1297-1306
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• 2012

본 논문에서는 77 GHz 차량용 레이더 시스템에 필요한 레이더 송신기를 설계하였다. 130 nm RF CMOS 공정을 이용하여 설계한 13 GHz 주파수 합성기로 6 체배기를 내장한 상용의 화합물 전력 증폭기를 구동하여 77 GHz 송신 신호를 발생시켰다. 13 GHz 주파수 합성기는 6 체배용 전력 증폭기를 구동하기 위해 4 dBm 출력을 내는 주입 잠금 버퍼를 내장하고 있다. 제작한 77 GHz 레이더 송신기 모듈은 주파수 조정 범위 내에서 출력 전력이 최소 13.99 dBm이고, 중심 주파수 대비 기준 스퍼의 크기는 -36.45 dBc이다. 또한, 76.5 GHz 중심 주파수의 1 MHz 오프셋에서 -81 dBc/Hz의 위상 잡음 특성을 보인다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.24.1-24.1
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• 2009

The zinc oxide (ZnO) material as the II-VI compound semiconductor is useful in various fields of device applications such as light-emitting diodes (LEDs), solar cells and gas sensors due to its wide direct band gap of 3.37eV and high exciton binding energy of 60meV at room temperature. In this study, the ZnO nanorods were deposited onto homogenous buffer layer/Si(100) substrates by a hydrothermal synthesis. The Effects of the buffer layer annealing and post annealing temperature on the structural and optical properties of ZnO nanorods grown by a hydrothermal synthesis were investigated. For the buffer layer annealing case, the annealed buffer layer surface became rougher with increasing of annealing temperature up to $750^{\circ}C$, while it was smoothed with more increasing of annealing temperature due to the evaporation of buffer layer. It was found that the roughest surface of buffer layer improved the structural and optical properties of ZnO nanorods. For the post annealing case, the hydrothermally grown ZnO nanorods were annealed with various temperatures ranging from 450 to $900^{\circ}C$. Similarly in the buffer layer annealing case, the post annealing enhanced the properties of ZnO nanorods with increasing of annealing temperature up to $750^{\circ}C$. However, it was degraded with further increasing of annealing temperature due to the violent movement of atoms and evaporation. Finally, the buffer layer annealing and post annealing treatment could efficiently improve the properties of hydrothermally grown ZnO nanorods. The morphology and structural properties of ZnO nanorods grown by the hydrothermal synthesis were measured by atomic force microscopy (AFM), field emission scanning electron microscopy (SEM), and x-ray diffraction (XRD). The optical properties were also analyzed by photoluminescence (PL) measurement.

• Journal of electromagnetic engineering and science
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• 제17권2호
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• pp.105-107
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• 2017

The self-biasing circuit through a feedback resistor is applied to a gallium nitride (GaN) distributed power amplifier (PA) monolithic microwave circuit (MMIC). The self-biasing circuit is a useful scheme for biasing depletion-mode compound semiconductor devices with a negative gate bias voltage, and is widely used for common source amplifiers. However, the self-biasing circuit is rarely used for PAs, because the large DC power dissipation of the feedback resistor results in the degradation of output power and power efficiency. In this study, the feasibility of applying a self-biasing circuit through a feedback resistor to a GaN PA MMIC is examined by using the high operation voltage of GaN high-electron mobility transistors. The measured results of the proposed GaN PA are the average output power of 41.1 dBm and the average power added efficiency of 12.2% over the 6-16 GHz band.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.990-994
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• 2005

II-VI족 화합물 반도체를 성장하기 위한 MBE 성장 조건으로서 성장 온도, flux 율, 성장률에 대해 연구하였다. 성장 온도, flux 율, 성장률은 각각 290 $^{\circ}C$, 2, 0.6 ${\mu}m$/hr로 조절되었다. 위와 같이 설정된 성장 조건에서 단결정 성장을 확인하기 위하여 ZnSe 박막을 성장하였다. 성장된 박막의 AFM 측정 결과, 박막의 표면은 비교적 거칠었으며 (RMS ${\sim}$ 2.9 nm) 이는 낮은 성장 온도, 빠른 성장률로 인한 것임을 알 수 있었다. 그리고 XRD 측정 결과는 박막의 두께가 임계 두께를 넘어서 격자 정수의 부정합이 완화되었음을 보여주었다. XRD를 이용한 비파괴 방법으로 전위 밀도를 구하기 위해 (002), (004), (115), (006) 면에 대해 XRD를 측정하여 박막 내 전위밀도를 구하였다. XRD 측정 결과를 이용하여 계산한 결과 전위 밀도는 8.30${\times}10^8$ dis/cm$^2$로 종래의 연구와 비슷한 수준의 박막이 구현되었음을 알 수 있었다.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1654-1659
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• 2014

Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

• 한국정보통신학회논문지
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• 제8권2호
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• pp.440-448
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• 2004

본 논문에서는 II-Vl족의 ZnTe 화합물반도체 태양전지를 제작하기 위하여 투명전극(AZO) 및 Buffer layer(ZnO)의 특성과 태양전지의 효율에 가장 큰 영향을 미치는 광흡수층의 에너지밴드갭을 줄이는 연구를 하였다. ZnTe박막은 Zn(Zinc)과 Te(Tellurium)를 co-sputtering법을 이용하여 증착하였다. ZnTe 박막은 Zn과 Te의 RF power를 각각 50W, 30W로 하여 10mTorr의 Ae 분위기에서 20$0^{\circ}C$의 기판온도로 제작되었으며, 이때의 에너지밴드갭은 1.73eV였다. 이렇게 제작된 박막을 진공상태에서 $400^{\circ}C$의 온도로 10초간 열처리하여 1.67eV의 에너지밴드갭을 얻을 수 있었고, 이때의 Zn과 Te의 비율은 32%:68%였다. 최적의 조건에서 태양전지는 6.85% (Voc:0.69V, Jsc:21.408㎃/$cm^2$, Fill Factor (FF):0.46)의 효율을 얻을 수 있었다.