• Journal of KIISE:Software and Applications
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• v.32 no.1
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• pp.62-73
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• 2005

Evolvable Hardware is the technique that obtains target function by adapting reconfigurable digital' devices to environment in real time using evolutionary computation. It opens the possibility of automatic design of hardware circuits but still has the limitation to produce complex circuits. In this paper, we have analyzed the fitness landscape of evolvable hardware and proposed a speciation technique of evolving diverse individuals simultaneously, proving the efficiency empirically. Also, we show that useful extra functions can be obtained by analyzing diverse circuits from the speciation technique.

• Journal of KIISE:Software and Applications
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• v.31 no.10
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• pp.1364-1373
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• 2004

Recently Evolvable Hardware (EHW) is widely studied to design effective hardware circuits that can reconfigure themselves according to the environment. However, it is still difficult to apply for complicated circuits because the search space increases exponentially as the complexity of hardware increases. To remedy this problem, this paper proposes a method to evolve complex hardware with a modular approach. The comparative experiments of some digital circuits with the conventional evolutionary approach indicate that the proposed method yields from 50 times to 1,000 times faster evolution and more optimized hardware.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.3
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• pp.206-215
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• 2005

In this paper, we propose a new design method of Genetic Algorithm Processor(GAP) and Evolvable Hardware(EHW). All sorts of creature evolve its structure or shape in order to adapt itself to environments. Evolutionary Computation based on the process of natural selection not only searches the quasi-optimal solution through the evolution process, but also changes the structure to get best results. On the other hand, Genetic Algorithm(GA) is good fur finding solutions of complex optimization problems. However, it has a major drawback, which is its slow execution speed when is implemented in software of a conventional computer. Parallel processing has been one approach to overcome the speed problem of GA. In a point of view of GA, long bit string length caused the system of GA to spend much time that clear up the problem. Evolvable Hardware refers to the automation of electronic circuit design through artificial evolution, and is currently increased with the interested topic in a research domain and an engineering methodology. The studies of EHW generally use the XC6200 of Xilinx. The structure of XC6200 can configure with gate unit. Each unit has connected up, down, right and left cell. But the products can't use because had sterilized. So this paper uses Vertex-E (XCV2000E). The cell of FPGA is made up of Configuration Logic Block (CLB) and can't reconfigure with gate unit. This paper uses Vertex-E is composed of the component as cell of XC6200 cell in VertexE

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.3
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• pp.133-144
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• 2000

Genetic Algorithm(GA) has been known as a method of solving large-scaled optimization problems with complex constraints in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementations of Genetic Algorithm Processors(GAP) are focused on in recent studies. In this paper, a hardware-oriented GA was proposed in order to save the hardware resources and to reduce the execution time of GAP. Based on steady-state model among continuos generation model, the proposed GA used modified tournament selection, as well as special survival condition, with replaced whenever the offspring's fitness is better than worse-fit parent's. The proposed algorithm shows more than 30% in convergence speed over the conventional algorithm in simulation. Finally, by employing the efficient pipeline parallelization and handshaking protocol in proposed GAP, above 30% of the computation speed-up can be achieved over survival-based GA which runs one million crossovers per second (1㎒), when device speed and size of application are taken into account on prototype. It would be used for high speed processing such of central processor of evolvable hardware, robot control and many optimization problems.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2944-2946
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• 1999

In this paper, digital circuit evolution is proposed as an intrinsic evolvable system. Evolutionary hardware is a reconfigurable one which adapt itself to the environment and evolve its structure to realize desired performance. By using special FPGA and genetic algorithm, we have made a prototype of intrinsic hardware evolution system. As an example for digital circuit evolution, full adder realization is performed. As the result of this, a very complex structure of digital circuit performing full adder was created. Analysis made on the hardware revealed that some undetermined circuits were developed.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.4
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• pp.265-276
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• 2004

Genetic Algorithm(GA), that is shown stable performance to find an optimal solution, has been used as a method of solving large-scaled optimization problems with complex constraints in various applications. Since it takes so much time to execute a long computation process for iterative evolution and adaptation. In this paper, a hardware-based adaptive GA was proposed to reduce the serious computation time of the evolutionary process and to improve the accuracy of convergence to optimal solution. The proposed GA, based on steady-state model among continuos generation model, performs an adaptive mutation process with consideration of the evolution flow and the population diversity. The drawback of the GA, premature convergence, was solved by the proposed adaptation. The Performance improvement of convergence accuracy for some kinds of problem and condition reached to 5-100% with equivalent convergence speed to high-speed algorithm. The proposed adaptive GAP(Genetic Algorithm Processor) was implemented on FPGA device Xilinx XCV2000E of EHW board for face recognition.

• International Journal of Aeronautical and Space Sciences
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• v.17 no.4
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• pp.467-475
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• 2016

Ultrasonic propagation imaging (UPI) has shown great potential for detection of impairments in complex structures and can be used in wide range of non-destructive evaluation and structural health monitoring applications. The software implementation of such algorithms showed a tendency in time-consumption with increment in scan area because the processor shares its resources with a number of programs running at the same time. This issue was addressed by using field programmable gate arrays (FPGA) that is a dedicated processing solution and used for high speed signal processing algorithms. For this purpose, we need an independent and flexible block of logic which can be used with continuously evolvable hardware based on FPGA. In this paper, we developed an FPGA-based ultrasonic propagation imaging system, where FPGA functions for both data acquisition system and real-time ultrasonic signal processing. The developed UPI system using FPGA board provides better cost-effectiveness and resolution than digitizers, and much faster signal processing time than CPU which was tested using basic ultrasonic propagation algorithms such as ultrasonic wave propagation imaging and multi-directional adjacent wave subtraction. Finally, a comparison of results for processing time between a CPU-based UPI system and the novel FPGA-based system were presented to justify the objective of this research.