• Proceedings of the Korea Information Processing Society Conference
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• 2004.11a
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• pp.203-206
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• 2004

본 논문은 SoC 환경에서 암호화 알고리즘의 처리 성능을 향상시키기 위해 각 노드의 실행 시간을 비교하여 하드웨어와 소프트웨어로 codesign 하였다. 암호화 알고리즘으로서는 DES와 SHA-1을 통합 설계하여 적용하였다. 본 논문에서의 codesign 방법을 altera의 excalibur에서 구현하여 실행 시간 및 메모리 크기 그리고 회로의 게이트 크기를 비교 대상으로 하였다. 수행 결과에 따른 분석에 의하면 세가지 비교 대상에 최적화하여 codesign 성능을 찾을 수 있었다.

• Journal of Korea Multimedia Society
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• v.2 no.4
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• pp.476-489
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• 1999

HW/SW codesign is integrated design of systems implemented using both hardware and software components. Many design tools has been developed to support this new paradigm, so far. Current codesign tools are not widely used as been expected because of variety problems - rapidly evolving technology, platform dependency, absence of standard specification method, inconsistent user interface, varying target system, different functionality In this paper, we propose a web-based distributed HW/SW codesign environment to remedy this kinds of problem. Our codesign environment has object-based 3 tier client/server architecture. It supports collaborative workspace through session service. Fully object-oriented design of user interface(OOUI) enables easy extension without change of user Interface. Furthermore it contains transaction server and security server for efficient and safe transfer of design data. To show a validity of our design, we developed prototype of web-based HW/SW codesign environment called WebCEDA. Our model of HW/SW codesign can be used for web-based generic CAD tools.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.120-123
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• 2000

In this paper, A target architecture and interface synthesizer are proposed for processor-embedded codesign. The target architecture has the form of ARM processor based on AMBA. The interface synthesizer automatically generates an interface circuit for the communication between HW and SW. A memory map is used as the communication channel and an interrupt-based interface is applied for synchronized communication between HW and SW modules. In order to verify the function and performance of proposed target architecture and the interface synthesizer, practical test example is applied. Experimental results show the proposed interface synthesizer functioned correctly in the HW/SW codesign environment.

• The KIPS Transactions:PartD
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• v.12D no.6 s.102
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• pp.863-868
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• 2005

Hardware and software codesign framework called PeaCE(Ptolemy extension as a Codesign Environment) was developed. It allows to express both data flow and control flow which is described as fFSM which extends traditional finite state machine. While the fFSM model provides lots of syntactic constructs for describing control flow, it has a lack of their formality and then difficulties in verifying the specification. In order to define the formal semantics of the fFSM, in this paper, firstly the hierarchical structure in the model is flattened and then the step semantics is defined. As a result, some important bugs such as race condition, ambiguous transition, and circulartransition can be formally detected in the model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9A
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• pp.1368-1376
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• 2000

This paper describes the codesign method for IS-95 based CDMA(Code Division Multiple Access). By codesign we mean to design hardware and software simultaneously. Codesign lead to reduction in design time, cost and power consumption. When we partition a system into hardware and software, some modules with longer processing time and larger power consumption are implemented using hardware and the remaining part is implemented using software. In proposed design, we design the synchronous accumulator of CDMA searcher in hardware and the other part in software, The hardware part is designed using VHDL, while software part is designed using GC(Generic C). We simulated and verified the system using COSSAP in SYNOPSYSTM. Experimentation showed the maximum 48.5% speed reduction compared with the design using software only.

• Journal of Korea Multimedia Society
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• v.8 no.1
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• pp.79-87
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• 2005

In e-commerce applications, a public key cryptosystem is an important and indispensible element for the basic security operations such as authentication, digital signaturing, and key distribution. In wired network environments, the public key infrastructure certificate, which is based on X.509 specification, has been widely used. On the other hand, it still remains difficult to use the certificate information in wireless network environments due to the inherent limitations of the hand-held devices such as low computational power and short battery life. In this paper, we facilitate a codesign approach by implementing a software public-key cryptosystem and classifying its internal computation overheads quantitatively using a software profiling technique. Moreover, we propose a method to analyze the profiled data and apply it to the problem of software/hardware partitioning in a codesign approach. As an illustrative example, we analyze the computational overheads of an EC-Elfagamal application and examine a critical computational path.

• The KIPS Transactions:PartA
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• v.12A no.7 s.97
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• pp.563-570
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• 2005

Hardware and software codesign framework called PeaCE(Ptolemy extension as a Cod sign Environment) allows to express both data flow and control flow. To formally verify an fFSM specification which expresses control flow in PeaCE, the step semantics of the model was defined. In this paper, we introduce the automatic verification tool developed by formal semantics of previous work. This tool uses the SMV as inner model checker md, through our tool, users can formally verify some important bugs such as race condition, ambiguous transition, and circulartransition without directly writing logical formulae.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.10
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• pp.11-20
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• 2002

This paper proposes a hardware/software codesign of the MLSE equalizer for GSM.GPRS systems. We analyze algorithms of the MLSE equalizer which consists of a channel estimator using the correlation method and the Viterbi processor. We estimate the computational complexity requirement based on the simulation of TI TMS320C5x DSP. We also estimate the gate count from the results of logic synthesis using the samsung 0.5㎛ standard cell library (STD80). Based on the results of the complexity estimation and gate count, we propose the efficient software/hardware codesign of the MLSE equalizer based on the results of the complexity estimation and gate count.

• Journal of Korea Multimedia Society
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• v.3 no.6
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• pp.661-673
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• 2000

In this paper, we propose a Web-based HW/SW Codesign Environment with Distributed Architecture (WebCEDA), then design and implement SpecCharts Specification Environment(ScSE) for specifying systems in WebCEDA. WebCEDA has 3-tier client/server architecture than can remedy disadvantages of existing codesign tools, such as platform dependency, difficulty of extension, absence of collaboraton environment. ScSE includes web interface, SpecCharts editor, HW/SW codesin application sever and SpecCharts translator. To verify the operation of ScSE, we specify several example system using SpecCharts editor, then translate it to VHDL using SpecCharts translator and simulate the translated VHDL codes on synopsys. As the results, we know that ScSE has correct operations, also obtain the following advantages, the reduction in system complexity and the natural abstract design.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.