• Journal of Communications and Networks
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• v.2 no.1
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• pp.69-75
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• 2000

A new frame synchronization confirmation technique using a pilot pattern of both uplink and downlink channels is proposed for W-CDMA (Wideband Code Division Multiple Access) system. It is shown that by using this technique, we can cancel the side lobe for autocorrelation functions of the frame synchronization words of pilot pattern have the maximum to-of-phase autocorrelation value "4" with two peak values equal in magnitude and opposite in polarity at zero and middle shifts. Due to this side lobe cancellation effect, therefore, the autocorrelation function of the frame synchronization words becomes ideal for the frame synchronization confirmation since double maximum correlation values equal in magnitude and opposite polarity at zero ad middle shifts can be achieved. This property can be used to double check frame synchronization timing and thus. improve the frame synchronization confirmation performance.

• Journal of Satellite, Information and Communications
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• v.4 no.1
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• pp.14-20
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• 2009

This paper describes synchronization concept and algorithm of the reverse DS-SS/TDMA control channel to handle satellite terminals which are distributed through the mission area. Military satellite control channel should have ECCM capabilities and handle more than several hundreds satcom terminals simultaneously. DS-SS/TDMA control channel can satisfy these demand but it spend much synchronization time. Proposed algorithm insert the preamble which is divided with several short sub bins prior to control data and use the parallel matched filtering searcher for each sub bin. As a result of the test, proposed algorithm can acquire most of control channel packet successfully within several milliseconds in severe jamming environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.2
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• pp.193-197
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• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.11-14
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• 1998

This paper introuces a new efficient method of synchronization acquisition which is the most important element in DS-CDMA system using the phase offset of binary code. This approach uses the binary code function which can easily estimate the phase offset from the received spreading waveforms which respect to the receiver-stored replica of the spreading code. This paper proposes the initial acquisition model with repeat error control device that is good for perfomance. The hardware is implemented by TMS320c30

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.43-48
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• 2010

In general, in order to reduce an initial cell searching time, W-CDMA systems adopt a three-step cell search scheme: slot synchronization, frame synchronization, and primary scrambling code identification. We consider the second step (frame synchronization), in which a coherent detection using P-SCH (primary synchronization channel) is possible. In this paper, we propose a new coherent detection scheme, where a first order recursive filter is used to enhance channel estimation performance. Computer simulation results indicate that the detection performance of the proposed scheme can be robust over large range of frequency offset.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.47 no.11
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• pp.812-820
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• 2019

The GNSS receiver for KSLV(Korea Space Launch Vehicle)-II provides real-time navigation data as well as precise time and time interval. The precise time signals provided by the GNSS receiver that can be used for the time synchronization between onboard systems, and between the onboard systems and ground stations have the forms of the 1PPS(One Pulse Per Second) and IRIG-B(Inter-Range Instrumentation Group Time Code B) which are synchronized with UTC(Coordinated Universal Time). A signal for timing faults also informs whether the time synchronization signals are available or not. This paper describes the time synchronization signals of the GNSS receiver for KSLV-II and their performance assessment.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.325-328
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• 2001

In this work, Cell search which is one of the important abilities of W-CDMA system in Reyleigh s fading channel is studied by using Cell Searcher of asynchronous IMT-2000 system(3GPP) and Cell - search simulation. For the methods of cell search to optimize codes, three stages are considered: 1) slot synchronization, 2) frame synchronization, and 3) scrambling code identification. It is found that key system parameters such as Primary Synchronization Channel (P-SCH), Secondary L Synchronization Channel(S-SCH), and Common Pilot Channel (CPCH) loading factor are optimized. It is noted that the smaller Optimal threshold value, the larger SNR of the received singnal. Therefore, It is important that the optimal threshold value is selected in the region of SNR

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.5
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• pp.400-410
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• 1988

In this paper, a fast synchronization system using SAW TDL matched filter and SAW recirculation loop not only for acquisition but also tracking in the direct sequence spread spectrum communication receiver in case of low SNR was designed and its characteristics were investigated. When signal of 16dB SNR was inputed at the receiver, the PN code of the receiver could be synchronized from the extracted signal for synchronization through SAW TDL matched filter and SAM recirculation loop for 30 recirculations. And the average synchronization time of this system was calculated. From the results, we found that this synchronization system could achieve faster synchronization of PN codes in the receiver under the circumstances of low SNR than that of using only matched filter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.8C
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• pp.697-708
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• 2010

In this paper, we compare the timing synchronization performance of the adaptive filter to that of the correlator in direct sequence spread spectrum (DS/SS) systems. The test variables used in the code synchronization are statistically analyzed for both schemes, and then the obtained results are used in calculating the detection and false alarm probabilities. Based on the derived probabilities, the synchronization performance is compared and the simulation is followed. Analysis and simulation results show that the correlator outperforms the adaptive filter under most synchronization environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.207-217
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• 1993

In this paper, knowing a priori probability of phase offset between transmitted codes and reference codes in the receiver, we construct the state diagram of acquisition process of the direct sequence spread-spectrum communication system using the expanding window search. The scannings are performed from the cell with higher probability code epoch synchronization to that with lower one. We expand window size from initial value by r times of its previous size in each search, construct the corresponding the state diagrams, and derive average synchronization time using the Markov process and Mason's gain formula. Average synchronization times versus number of search n and detection probability $P_d$ are calculated.