• ETRI Journal
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• v.18 no.4
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• pp.215-227
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• 1997

We propose a new method to eliminate completely the redundant elements in a CDMA (code division multiple access) mobile system. First, we define multilevel logic operation (MLO), which is a new concept to deal with the multilevel logic signals. We prove that the conventional binary logic concept is a subset of the MLO concept. The multilevel logic signal can be directly controlled by using this MLO in place of the binary operation. We applied the MLO to the CDMA base station modulator (BSM) in order to reduce the hardware complexity. In the case of a 3-sectorized cell, this method helps reduce the complexity down the level of below 1% of the conventional CDMA BSM for spreading and filtering, and to 50% for Walsh covering.

• The KIPS Transactions:PartC
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• v.10C no.1
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• pp.27-32
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• 2003

An efficient soft-decision decoding algorithm for binary block codes it proposed. The proposed soft-decision decoding algorithm is implemented by a series of hard-decision decoding process. By the hard-decision decoding result, the candidate codewords are efficiently searched for A new decoding method, which prevents the missing of the candidate codeword, is proposed. Also, the method fir reducing complexity is developed. This method removes the practical complexity increase caused by the improved algorithm. There facts are confirmed by the simulation results for binary (63, 36) BCH code.

• Journal of Sensor Science and Technology
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• v.24 no.3
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.

• Proceedings of the IEEK Conference
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• summer
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• pp.137-142
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• 2004

In this paper, we propose a new scheme for geometry coding of three-dimensional (3-D) mesh models using a fixed spectral basis. In order to code the mesh geometry information, we generate a fixed spectral basis using the dual graph derived from the 3-D mesh topology. After we partition a 3-D mesh model into several independent sub-meshes to reduce coding complexity, the mesh geometry information is projected onto the generated orthonormal bases which are the eigenvectors of the Laplacian matrix of the 3-D mesh. Finally, spectral coefficients are coded by a quantizer and a variable length coder. The proposed scheme can not only overcome difficulty of generating a fixed spectral basis, but also reduce coding complexity. Moreover, we can provide an efficient multi-resolution representation of 3-D meshes.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.153-162
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• 1995

When vector quantization is used in low rate image coding (e.g., R<0.5), the primary problem is the tremendous computational complexity which is required to search the whole codebook to find the closest codevector to an input vector. Since the number of code vectors in a vector quantizer is given by an exponential function of the dimension. i.e., L=2$^{nR}$ where Rn. To alleviate this problem, a multiple shell structure of hypercube feature maps (MSSHFM) is proposed. A binary HFM of k-dimension is composed of nodes at hypercube vertices and a multiple shell architecture is constructed by surrounding the k-dimensional hfm with a (k+1)-dimensional HFM. Such a multiple shell construction of nodes inherently has a complete tree structure in it and an efficient partial search scheme can be applied with drastically reduced computational complexity, computer simulations of still image coding were conducted and the validity of the proposed method has been verified.

• Journal of Communications and Networks
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• v.18 no.3
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• pp.439-445
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• 2016

In this paper, we consider subcarrier-index modulation (SIM) for precoded orthogonal frequency division multiplexing (OFDM) with a few activated subcarriers per user and its generalization to multi-carrier multiple access systems. The resulting multiple access is called sparse index multiple access (SIMA). SIMA can be considered as a combination of multi-carrier code division multiple access (MC-CDMA) and SIM. Thus, SIMA is able to exploit a path diversity gain by (random) spreading over multiple carriers as MC-CDMA. To detect multiple users' signals, a low-complexity detection method is proposed by exploiting the notion of compressive sensing (CS). The derived low-complexity detection method is based on the orthogonal matching pursuit (OMP) algorithm, which is one of greedy algorithms used to estimate sparse signals in CS. From simulation results, we can observe that SIMA can perform better than MC-CDMA when the ratio of the number of users to the number of multi-carrier is low.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06a
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• pp.1104-1111
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• 1994

Code Excited Linear Prediction(CELP) as a speech coder exhibits good performance at data rates below 4.8 kbps. The major drawback to CELP type coders is their large amount of computation. In this paper, we propose a new pitch search method that preserves the quality of the CELP vocoder with reduced complexity. The basic idea is to restrict the pitch searching range by estimating the preliminary pitches. Applying the proposed method to the CELP vocoder, we can get approximately 87% complexity reduction in the pitch search.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06a
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• pp.904-911
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• 1994

Code Excited Linear Prediction (CELP) speech coders exhibit good performance at data rates below 4.8 kbps. The major drawback to CELP type coders is their many computation. In this paper, we propose a new pitch search method that preserves the quality of the CELP vocoder with reducing complexity. The basic idea is to apply the preprocessing technique beforehand grasping the autocorrelation property of speech waveform. By using the proposed method, we can get approximately 77% complexity reduction in the pitch search.

• Journal of Communications and Networks
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• v.11 no.1
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• pp.11-19
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• 2009

Multicarrier direct sequence code division multiple access (MC DS-CDMA) is an attractive technique for achieving high data rate transmission. This is valid regardless of whether or not the potentially large peak-to-average power ratio (PAPR) is an important factor for its application. On the other hand, code select CDMA (CS-CDMA) is an attractive technique with constant amplitude transmission of multicode signal regardless of subchannels. This is achieved by introducing a code select method. In this paper, we propose a new multiple access scheme based on the combination of MC DS-CDMA and CS-CDMA. The proposed scheme, which we call MC CS-CDMA, includes as special cases the subclasses of MC DS-CDMA and CS-CDMA. This paper investigates the performance of these systems over a multipath frequency selective fading channel using a RAKE receiver with maximal ratio combiner. In addition, the PAPR of the proposed system is compared with that of both MC DS-CDMA and CS-CDMA. Simulation results demonstrate that the proposed system provides better PAPR reduction than MC DS-CDMA, at the expense of the complexity of the receiver and the number of available users. The numerical result demonstrates that the proposed system has better performance than MC DS-CDMA due to the increased processing gain and time diversity gain.

• Journal of the Korea Society of Computer and Information
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• v.13 no.3
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• pp.45-55
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• 2008

Due to the increasing complexity of embedded system design, automatic code generation of embedded software and hardware-software co-design methodologies are gaining great interest from industries and academia. Such an automatic design methodologies are always demanding a formal system specification languages for defining designer's idea clearly and precisely. In this paper, we propose automatic embedded C code generation from SDL (Specification and Description Language, ITU-T recommended the SDL as a standard system description language) with considering a real-time uC/OS-II operating system. Our automatic embedded C code generator is expected to provide a fast specification, verification and performance evaluation platform for embedded software designs.