• Title/Summary/Keyword: code complexity

Search Result 589, Processing Time 0.027 seconds

Hardware implementation of a SOVA decoder for the 3GPP complied Turbo code (3GPP 규격의 터보 복호기 구현을 위한 SOVA 복호기의 하드웨어 구현)

  • 김주민;고태환;이원철;정덕진
    • Proceedings of the IEEK Conference
    • /
    • 2001.06a
    • /
    • pp.205-208
    • /
    • 2001
  • According to the IMT-2000 specification of 3GPP(3rd Generation Partnership Project) and 3GPP2, Turbo codes is selected as a FEC(forward error correction) code for even higher reliable data communication. In 3GPP complied IMT-2000 system, channel coding under consideration is the selective use of convolutional coding and Turbo codes of 1/3 code rate with 4 constraint length. Suggesting a new path metric normalization method, we achieved a low complexity and high performance SOVA decoder for Turbo Codes, Further more, we analyze the decoding performance with respect to update depth and find out the optimal value of it by using computer simulation. Based on the simulation result, we designed a SOVA decoder using VHDL and implemented it into the Altera EPF10K100GC503FPGA.

  • PDF

Soft-Decision-and-Forward Protocol for Cooperative Communication Networks with Multiple Antennas

  • Yang, Jae-Dong;Song, Kyoung-Young;No, Jong-Seon;Shin, Dong-Joan
    • Journal of Communications and Networks
    • /
    • v.13 no.3
    • /
    • pp.257-265
    • /
    • 2011
  • In this paper, a cooperative relaying protocol called soft-decision-and-forward (SDF) with multiple antennas in each node is introduced. SDF protocol exploits the soft decision source symbol values from the received signal at the relay node. For orthogonal transmission (OT), orthogonal codes including Alamouti code are used and for non-orthogonal transmission (NT), distributed space-time codes are designed by using a quasi-orthogonal space-time block code. The optimal maximum likelihood (ML) decoders for the proposed protocol with low decoding complexity are proposed. For OT, the ML decoders are derived as symbolwise decoders while for NT, the ML decoders are derived as pairwise decoders. It can be seen through simulations that SDF protocol outperforms AF protocol for both OT and NT.

Split LDPC Codes for Hybrid ARQ

  • Joo, Hyeong-Gun;Hong, Song-Nam;Shin, Dong-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.32 no.10C
    • /
    • pp.942-949
    • /
    • 2007
  • In this paper, we propose a new rate-control scheme, called splining, to construct low-rate codes from high-rate codes by splitting rows of the parity-check matrices of LDPC codes, which can construct rate-compatible LDPC codes having good initial transmission performance. Good low-rate codes can be constructed by making the number of distinct check node degrees as small as possible after splitting. The proposed scheme achieves good cycle property, low decoding complexity, and fast convergence speed, especially compared to the puncturing. Especially, rate-compatible repeat accumulate-type LDPC (RA-Type LDPC) code is constructed using splitting, which covers the code rates from 1/3 to 4/5. Through simulation it is shown that this code outperforms other rate-compatible RA-Type LDPC codes for all rates and can be decoded conveniently and efficiently.

Logic gate implementation of constant amplitude coded CS/CDMA transmitter (정포락선 부호화된 CS-CDMA 송신기의 논리 게이트를 이용한 구현)

  • 김성필;류형직;김명진;오종갑
    • Proceedings of the IEEK Conference
    • /
    • 2003.11c
    • /
    • pp.281-284
    • /
    • 2003
  • Multi-code CDMA is an appropriate scheme for transmitting high rate data. However, dynamic range of the signal is large, and power amplifier with good linearity is required. Code select CDMA (CS/CDMA) is a variation of multi-code CDMA scheme that ensures constant amplitude transmission. In CS/CDMA input data selects multiple orthogonal codes, and sum of these selected codes are MPSK modulated to convert multi-level symbol into different carrier phases. CS/CDMA system employs level clipping to limit the number of levels at the output symbol to avoid hish density of signal constellation. In our previous work we showed that by encoding input data of CS/CDMA amplitude of the output symbol can be made constant. With this coding scheme, level clipping is not necessary and the output signal can be BPSK modulated for transmission. In this paper we show that the constant amplitude coded(CA-) CS/CDMA transmitter can be implemented using only logic gates, and the hardware complexity is very low. In the proposed transmitter architecture there is no apparent redundant encoder block which plays a major role in the constant amplitude coded CS/CDMA.

  • PDF

Area-Efficient Semi-Parallel Encoding Structure for Long Polar Codes (긴 극 부호를 위한 저 면적 부분 병렬 극 부호 부호기 설계)

  • Shin, Yerin;Choi, Soyeon;Yoo, Hoyoung
    • Journal of IKEEE
    • /
    • v.23 no.4
    • /
    • pp.1288-1294
    • /
    • 2019
  • The channel-achieving property made the polar code show to advantage as an error-correcting code. However, sufficient error-correction performance shows the asymptotic property that is achieved when the length of the code is long. Therefore, efficient architecture is needed to realize the implementation of very-large-scale integration for the case of long input data. Although the most basic fully parallel encoder is intuitive and easy to implement, it is not suitable for long polar codes because of the high hardware complexity. Complementing this, a partially parallel encoder was proposed which has an excellent result in terms of hardware area. Nevertheless, this method has not been completely generalized and has the disadvantage that different architectures appear depending on the hardware designer. In this paper, we propose a hardware design scheme that applies the proposed systematic approach which is optimized for bit-dimension permutations. By applying this solution, it is possible to design a generalized partially parallel encoder for long polar codes with the same intuitive architecture as a fully parallel encoder.

Complexity reduced partial transmit sequence for PAPR reduction and performance analysis with nonlinear high power amplifier in MC-CDMA (MC-CDMA에서 PAPR 감소를 위한 복잡도가 감소된 부분전송열 기법과 비선형 고출력 증폭기에 의한 성능 분석)

  • 강군석;김수영;오덕길;김재명
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.28 no.5A
    • /
    • pp.305-315
    • /
    • 2003
  • MC-CDMA(Multicarrier code division multiple access), which is based on a combination of OFDM(orthogonal frequency division multiplexing) and CDMA(code division multiple access), has gained a lot of interests in wireless multimedia communications, as high speed data transmission is required for mobile services. MC-CDMA has many advantages for broadband high speed data transmission in multipath environment because it can offer both advantages of the CDMA and the OFDM. However, A high PAPR(peak to average power ratio) problem, which is a major drawback of OFDM, is also shown in the MC-CDMA. In this paper, we propose a new phase factor optimization scheme to reduce complexity in PTS(partial transmit sequence) to reduce PAPR. We also analyze the performance of the MC-CDMA with various PTS schemes to investigate the relations between PAPR characteristics and effect of nonlinear distortion of a high power amplifier. Our simulation results reveal that the proposed PTS scheme reduces PAPR about 0.2∼0.5 dB even with 25% reduced- complexity compared to the conventional scheme.

Frequency Domain Channel Estimation for MIMO SC-FDMA Systems with CDM Pilots

  • Kim, Hyun-Myung;Kim, Dongsik;Kim, Tae-Kyoung;Im, Gi-Hong
    • Journal of Communications and Networks
    • /
    • v.16 no.4
    • /
    • pp.447-457
    • /
    • 2014
  • In this paper, we investigate the frequency domain channel estimation for multiple-input multiple-output (MIMO) single-carrier frequency-division multiple-access (SC-FDMA) systems. In MIMO SC-FDMA, code-division multiplexed (CDM) pilots such as cyclic-shifted Zadoff-Chu sequences have been adopted for channel estimation. However, most frequency domain channel estimation schemes were developed based on frequency-division multiplexing of pilots. We first develop a channel estimation error model by using CDM pilots, and then analyze the mean-square error (MSE) of various minimum MSE (MMSE) frequency domain channel estimation techniques. We show that the cascaded one-dimensional robust MMSE (C1D-RMMSE) technique is complexity-efficient, but it suffers from performance degradation due to the channel correlation mismatch when compared to the two-dimensional MMSE (2D-MMSE) technique. To improve the performance of C1D-RMMSE, we design a robust iterative channel estimation (RITCE) with a frequency replacement (FR) algorithm. After deriving the MSE of iterative channel estimation, we optimize the FR algorithm in terms of the MSE. Then, a low-complexity adaptation method is proposed for practical MIMO SC-FDMA systems, wherein FR is performed according to the reliability of the data estimates. Simulation results show that the proposed RITCE technique effectively improves the performance of C1D-RMMSE, thus providing a better performance-complexity tradeoff than 2D-MMSE.

Multilevel Modulation Codes for Holographic Data Storage (홀로그래픽 데이터 저장장치에서의 멀티레벨 변조부호)

  • Jeong, Seongkwon;Lee, Jaejin
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.52 no.9
    • /
    • pp.13-18
    • /
    • 2015
  • The mutilevel holographic data storage offers considerable advantage for capacity, since it can store more than one bit per pixel. In this paper, we search the number of codewords for each code depending on three conditions: (1) the number of levels, (2) the number of pixels in a codeword, and (3) the minimum Euclidean distance of a code. Increasing the number of levels per pixel creates more capacity, while causing more errors, by reducing the noise margin. Increasing the number of pixels in a codeword can increase the code rate, which means more capacity, but increases the complexity of the encoder/decoder of the code. Increasing the minimum distance of a code reduces the detection error, while reducing the code rate of the code. In such a fashion, a system design will always have pros and cons, but our task is to find out an effective one under the given conditions for the system requirements. Therefore, the numbers we searched can provide some guidelines for effective code design.

STBC Detection Algorithm Using Double-Decision-Feedback Scheme in Time-Varying Rayleigh-Fading Channel (시변 레일리 페이딩 채널에서 이중 판정 궤환 방식을 이용한 STBC 검출 알고리즘)

  • Park, Sung-Joon;Heo, Seo-Weon;Lee, Ho-Kyoung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.18 no.11
    • /
    • pp.1237-1242
    • /
    • 2007
  • In this paper, we study STBC(Space Time Block Code) detection scheme in time varying Rayleigh fading channel. When the channel is varying during the time duration of STBC, the channel matrix of orthogonal STBC is not orthogonal. To get the optimum reception performance in this channel, joint ML detection scheme may be used, however this scheme requires high computation complexity. Decision feedback scheme is proposed to reduce the computation complexity with less reception performance. In this paper, we propose a novel STBC detection algorithm using double decision feedback which is less complex than the joint ML scheme and outperforms the conventional decision feedback scheme.

A New Concatenation Scheme of Serial Concatenated Convolutional Codes (직렬연접 길쌈부호의 새로운 연접방법)

  • Bae, Sang-Jae;Ju, Eon-Gyeong
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.39 no.3
    • /
    • pp.125-131
    • /
    • 2002
  • In this paper, a new concatenation scheme of serial concatenated convolutional codes is proposed and the performance analyzed. In the proposed scheme, each of information and parity bits of outer code is entered into inner code through interleaver and deinterleaver. Therefore, the interleaver size is same as the length of input frame. Since the interleaver size of proposed type is reduced to half of the conventional Benedetto type, the interleaver delay time required for iterative decoding is reduced. In addition the multiplexer and demultiplexer are not used in the decoder of the proposed type, the complexity of decoder can be also reduced. As results of simulation, the performance of proposed type shows the better error performance as compared to that of the conventional Benedetto type in case of the same interleaver size. And it can be observed that the difference of BER performance is increased with the increase of Eb/No. In case of the same length of input frame, the proposed type shows almost same performance with Benedetto type despite that the interleaver size is reduced by half.