• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1481-1494
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• 1997

In hard real-time systems, a timing fault may yield catastrophic results. Dynamic scheduling provides the flexibility to compensate for unexpected events at runtime; however, scheduling overhead at runtime is relatively large, constraining both the accuracy of the timing and the complexity of the scheduling analysis. In contrast, static scheduling need not have any runtime overhead. Thus, it has the potential to guarantee the precise time at which each instruction implementing a control action will execute. This paper presents a new approach to the problem of analyzing high-level language code, augmented by arbitrary before and after timing constraints, to provide a valid static schedule. Our technique is based on instruction-level complier code scheduling and timing analysis, and can ensure the timing of control operations to within a single instruction clock cycle. Because the search space for a valid static schedule is very large, a novel adaptive genetic search algorithm was developed.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06a
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• pp.228-229
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• 2010

• The Transactions of the Korea Information Processing Society
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• v.6 no.11
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• pp.3124-3130
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• 1999

A duplex system enhances reliability by tolerating faults through spatial redundancy. Faults can be detected by duplicating identical tasks in pairs of modules. However, this kind of systems cannot even detect the fault if it occurs coincidently due to either malfunctions of common component such as power supply and clock or due to such environmental disruption as EMI. In the paper, we propose a method to reduce those effects of coincident faults in the duplex controller computer. Specifically, a duplex system tolerates coincident faults by using a sophistication sequencing of scheduling technique with certain timing redundancy. In particular when all tasks should be completed in the sense of real-time, the suggested scheduling method works properly to minimize the probability of faulty tasks due to coincident fault without missing the timing constraints.

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.118-128
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• 1996

In safety critical hard real-time systems, a timing fault may yield catastrophic results. In order to eliminate the timing faults from the fast responsive real-time control systems, it is necessary to schedule a code based on high precision timing analysis. Further, the schedulability enhancement by having multiple processors is of wide spread interest. However, although an instruction level parallel processing is quite effective to improve the schedulability of such a system, none of the real-time applications employ instruction level parallel scheduling techniques because most of the real-time scheduling models have not been designed for fine-grain execution. In this paper, we present a timing constraint model specifying high precision timing constraints, and a practical approach for constructing static schedules for a VLIW execution model. The new model and analysis can guarantee timing accuracy to within a single machine clock cycle.

• ETRI Journal
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• v.28 no.1
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.677-680
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• 2003

In this paper, the analysis of practical end-to-end delay in worst case is performed for distributed control system considering the implementation of the system. The control system delay is composed of the delay caused by multi-task scheduling of operating system, the delay caused by network communication, and the delay caused by the asynchronous between them. Through simulation tests based on CAN(Controller Area Network), the proposed end-to-end delay in worst case is validated. Additionally, online clock synchronization algorithm is proposed here for the control system. Through another simulation test, the online algorithm is proved to have better performance than offline one in the view of network bandwidth utilization.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.49-52
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• 2001

This paper presents a FPGA Implementation of wavelet-based CODEC, which can compress 2-dimensional image. For real-time processing, a scheduling method of input image data is proposed and a new structure of MAC(multiplier-accumulator) is proposed for wavelet transforms. Also this study proposes global pipelining structure of wavelet CODEC and efficient buffering method at interfaces between each module with different clock frequency.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.121-124
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• 2000

Goal of this Paper is to design and develop core kernel components f3r single processor real-time system, which include real-time schedulers, synchronization mechanism, IPC, message passing, and clock & timer. The goal also contains the basic researches on dynamic load balancing and scheduling which provide mechanism for the distributed information processing and efficient resource sharing among various information appliances based on network.

• Proceedings of the Korea Multimedia Society Conference
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• 2001.06a
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• pp.219-222
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• 2001

본 연구의 내용은 실시간 서비스 트래픽, 즉 보장형 서비스를 위한 스케줄링 알고리즘들에 대한 성능분석에 대한 연구이다. 특히 실시간 데이터 전송의 경우, 작은 지연 시간을 요구하면서 안정된 QoS를 요구하고 있다. 기존에 알려진 FQ, WFQ, WF2Q, Virtual Clock 스케줄링 알고리즘들을 사용해서 대기 큐의 수학적 모델이 아닌 시뮬레이션 도구를 사용해서, 지연에 민감한 보장형 서비스 트래픽에 대한 시간 복잡도, 공정성, 처리율 측면으로 성능을 분석하였다.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.716-719
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• 1999

In this paper, a real-time control system for robot manipulator is implemented using real-time operating system with capabilities of multitasking, intertask communication and synchronization, event-driven, priority-driven scheduling, real-time clock control, etc. The hardware system with VME bus and related devices is developed and applied to implement a dynamic learning control scheme for robot manipulator. Real-time performance of the proposed dynamic learning controller is tested for tasks of tracking moving objects and compared with the conventional servo controller.