• 한국통신학회논문지
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• 제23권4호
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• pp.1100-1112
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• 1998

본 연구에서 망동기 시스템의 동기 기준 클럭과 시스템 클럭간에 발생하는 위상 오차를 최소화하기 위한 새로운 위상 오차 검출방식이 제안되었고 이 방식을 디지털 처리 위상 동기 루프(digital processing phase locked loop:DP-PLL) 시스템에 적용하였다. 두 클럭간에 발생하는 위상 오차는 지연된 n-탭 상승 에지 클럭으로 구성한 위상 오차 검출기에 의해 위상 오차 변이 (PEV:Phase Error Variation)로 출력된다. 위상 오차 변이는 5ns해상도로 검출되며 검출된 위상 오차 변이는 알고리즘에 의해 최적의 D/A변환기 계수를 추적하면서 위상 동기를 유지한다. 실험결과 위상 검출기는 빠르고 정확한 위상 추적 특성을 갖고 있으며 루프제어 알고리즘은 우수한 지터 억압 특성을 나타내었다.

• 한국전자통신학회논문지
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• 제7권2호
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• pp.327-332
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• 2012

본 논문에서는 관측소 지리적 위치에 의한 대류권 파라미터에 따른 위성 클럭오차 특성을 분석한 것으로 PANDA 소프트웨어를 이용하여 관측소 거리의 간격에 따른 GPS 위성 클럭오차에 따른 정밀단독측위의 성능을 연구하여 결과를 제시하였다. 분석 결과에 의하면 거리의 간격이 200km 이하인 경우에는 대류권 파라미터와 위성 시계 오차 파라미터의 관련성이 크며, 최대 0.8ns의 클럭 오차를 발생하였다. 또한 거리의 간격이 500km이상인 경우에는 위성 클럭 오차와 대류권 파라미터의 관련성이 현저하게 감소됨을 알 수 있었다.

• 대한전자공학회논문지SD
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• 제44권12호
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• pp.37-42
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• 2007

클락 그리드 네트워크(Clock Grid Network)는 대부분의 고속 마이크로 프로세서에서 클락 스큐를 줄이기 위한 일반적인 방법이다. 본 논문은 클락 그리드의 모델링과 분석을 위해서 S-파라미터(Scattering Parameter)를 사용한 새로운 효과적인 방법을 제안한다. 또한, 그리드 사이즈와 와이어(wire) 폭이 그리드의 클락 스큐에 미치는 영향을 제시한다. 본 논문에서 클락 그리드의 상호 연결은 RC 수동소자에 의해서 모델화 되고, 제안된 방법의 결과는 Hspice의 시뮬레이션 결과와 비교해서 10 % 내의 오차를 보여준다.

• Journal of Positioning, Navigation, and Timing
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• 제12권3호
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• pp.215-228
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• 2023

The State Space Representation (SSR) method provides individual corrections for each Global Navigation Satellite System (GNSS) error components. This method can lead to less bandwidth for transmission and allows selective use of each correction. Precise Point Positioning (PPP) - Real-Time Kinematic (RTK) is one of the carrier-based precise positioning techniques using SSR correction. This technique enables high-precision positioning with a fast convergence time by providing atmospheric correction as well as satellite orbit and clock correction. Currently, the positioning service that supports PPP-RTK technology is the Quazi-Zenith Satellite System Centimeter Level Augmentation System (QZSS CLAS) in Japan. A system that provides correction for each GNSS error component, such as QZSS CLAS, requires monitoring of each error component to provide reliable correction and integrity information to the user. In this study, we conducted an analysis of the performance of residual error bounding for each error component. To assess this performance, we utilized the correction and quality indicators provided by QZSS CLAS. Performance analyses included the range domain, dispersive part, non-dispersive part, and satellite orbit/clock part. The residual root mean square (RMS) of CLAS correction for the range domain approximated 0.0369 m, and the residual RMS for both dispersive and non-dispersive components is around 0.0363 m. It has also been confirmed that the residual errors are properly bounded by the integrity parameters. However, the satellite orbit and clock part have a larger residual of about 0.6508 m, and it was confirmed that this residual was not bounded by the integrity parameters. Users who rely solely on satellite orbit and clock correction, particularly maritime users, thus should exercise caution when utilizing QZSS CLAS.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.168-176
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• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.

• 전자공학회논문지D
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• 제34D권1호
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• pp.30-34
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• 1997

An improved clock-feedthrough compensation scheme for switche dcurrent system is proposed. Both the signal dependent and the constant clock-feedthrough terms are cancelled by using both NMOS and PMOS current samplers and by adopting a source replication technique. The proposed current memory cell was fabricated with 0.6$\mu$m CMOS process. Both experimental and theoretical results on clock-feedthrough error reveal substantial reduction over the existing compensation schemes.

• 한국정보통신학회논문지
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• 제8권2호
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• pp.245-249
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• 2004

본 논문에서는 대역제한필터(BL-PSF)를 이용하는 OFDM/QPSK-DMR 시스템에 적합한 클럭 복원 알고리즘을 제안하고 OFDM/QPSK-DMR 시스템과 단일 주파수방식의 DMR 시스템의 클럭 위상에러분산을 비교 분석하였다. 기존 Windowing을 적용하는 OFDM/QPSK-DMR 시스템은 수신 클럭의 위상을 동기 시키기 위해 훈련심볼 또는 CP(Cyclic Prefix)등의 잉여 데이터를 사용하나 본 논문의 DMR 시스템은 전송효율을 향상시키기 위해 잉여 데이터를 삽입하지 않고 단일 주파수방식의 클럭복조방식을 채택하였다. 이 방식은 간단하게 구현할 수 있는 장점을 갖는다. 제안한 클럭 복원 알고리즘은 AWGN 환경에서 단일 주파수방식의 DMR 시스템과 성능 열화 없이 동일한 클럭 위상 에러 분산값을 갖는 것을 시뮬레이션 결과로 확인하였다.

• 제어로봇시스템학회논문지
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• 제21권7호
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• pp.669-676
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• 2015

In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

• 제어로봇시스템학회논문지
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• 제7권6호
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• pp.550-557
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• 2001

There are several applications and error analysis methods using GPS(Global Positioning System) In most analysis positioning and timing errors are represented as the multiplication of DOP(Dilution Of Precision) and measurement errors, which are affected by the receiver and measurement type. Therefore, lots of DOPs are defined and used to analyze and predict the performance of positioning and timing systems. In this paper, the relationships between these DOPs are investigated in detail, The relationships between GDOP(Geometric DOP), PDOP(Position DOP) and TDOP(Time DOP) in the absolute positioning are de-rived. Using these relationships, the affect of clock bias is analyzed. The relationships between RGDOP(Relative DOP) and PDOP are also derived in relative positioning where the single difference and double dif-ference techniques are used. From the results, it is expected that using the common clock will give better performance when the single difference technique is used while the effects of clock is eliminate when the double difference technique is used. Finally, the error analyses of dual frequency receivers show that the narrow lane measurements give more accurate results than wide line of or L1. L2 independent measurements.