• Molecules and Cells
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• v.25 no.4
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• pp.559-565
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• 2008

Members of the TGA family of basic domain/leucine zipper transcription factors regulate defense genes through physical interaction with NON-EXPRESSOR OF PR1 (NPR1). Of the seven TGA family members, TGA4/octopine synthase (ocs)-element-binding factor 4 (OBF4) is the least understood. Here we present evidence for a novel function of OBF4 as a regulator of flowering. We identified CONSTANS (CO), a positive regulator of floral induction, as an OBF4-interacting protein, in a yeast two-hybrid library screen. OBF4 interacts with the B-box region of CO. The abundance of OBF4 mRNA cycles with a 24 h rhythm under both long-day (LD) and short-day (SD) conditions, with significantly higher levels during the night than during the day. Electrophoretic mobility shift assays revealed that OBF4 binds to the promoter of the FLOWERING LOCUS T (FT) gene, a direct target of CO. We also found that, like CO and FT, an OBF4:GUS construct was prominently expressed in the vascular tissues of leaf, indicating that OBF4 can regulate FT expression through the formation of a protein complex with CO. Taken together, our results suggest that OBF4 may act as a link between defense responses and flowering.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.66-72
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• 2014

Histogram of oriented gradient (HOG) feature is widely used in vision-based pedestrian detection. The interpolation is the most important technique in HOG feature calculation to provide high detection rate. In interpolation technique of HOG feature calculation, two nearest orientation bins to gradient orientation for each pixel and the corresponding weights are required. In this paper, therefore, an efficient gradient orientation bin and weight calculation circuit for HOG feature is proposed. In the proposed circuit, pre-calculated values are defined in tables to avoid the operations of tangent function and division, and the size of tables is minimized by utilizing the characteristics of tangent function and weights for each gradient orientation. Pipeline architecture is adopted to the proposed circuit to accelerate the processing speed, and orientation bins and the corresponding weights for each pixel are calculated in two clock cycles by applying efficient coarse and fine search schemes. Since the proposed circuit calculates gradient orientation for each pixel with the interval of $1^{\circ}$ and determines both orientation bins and weights required in interpolation technique, it can be utilized in HOG feature calculation to support interpolation technique to provide high detection rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.431-435
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• 2011

This paper presents optimized searching technique to improve the performance of H.264/AVC. The proposed CAVLC encoder uses forward and backward searching algorithm to compute the parameters. By zero-block skipping technique and pipelined scheduling, the proposed CAVLC encoder can obtain better performance. The experimental result shows that the proposed architecture needs only 66.6 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 13.8% than that of previous designs. The proposed CAVLC encoder was implemented using VerilogHDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 15.6K with 125Mhz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.2
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• pp.201-211
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• 2012

This paper addresses a Full Disk Encryption hardware processor for SATA HDD in a single FPGA design, and shows its experimental result using an FPGA board. The proposed processor mainly consists of two blocks: the first block processes XTS-AES block cipher which is the IEEE P1619 standard of storage media encryption and the second block executes the interface between SATA Host (PC) and Device (HDD). To minimize the performance degradation, we designed the XTS-AES block with the 4-stage pipelined structure which can process a 128-bit block per 4 clock cycles and has 4.8Gbps (max) performance. Also, we implemented the proposed design with Xilinx ML507 FPGA board and our experiment showed 140MB/sec read/write speed in Windows XP 32-bit and a SATA II HDD. This performance is almost equivalent with the speed of the direct SATA connection without FDE devices, hence our proposed processor is very suitable for SATA HDD Full Disk Encryption environments.

• Journal of Ginseng Research
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• v.45 no.1
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• pp.183-190
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• 2021

Background: The circadian rhythm is the internal clock that controls sleep-wake cycles, metabolism, cognition, and several processes in the body, and its disruption has been associated with aging. The differentiated embryo chondrocyte (Dec) gene is related to circadian rhythm. To our knowledge, there are no reports of the relationship between dec gene expression and KRG effect. Therefore, we treated Dec gene knockout (KO) aging mice with KRG to study anti-aging related effects and possible mechanisms. Methods: We evaluated KRG and expression of Dec genes in an ototoxicity model. Dec genes expression in livers of aging mice was further analyzed. Then, we assessed the effects of DEC KO on hearing function in mice by ABR. Finally, we performed DNA microarray to identify KRG-related gene expression changes in mouse liver and assessed the results using KEGG analysis. Results: KRG decreased the expression of Dec genes in ototoxicity model, which may contribute to its anti-aging efficacy. Moreover, KRG suppressed Dec genes expression in liver of wild type indicating inhibition of senescence. ABR test indicated that KRG improved auditory function in aging mouse, demonstrating KRG efficacy on aging related diseases. Conclusion: Finally, in KEGG analysis of 238 genes that were activated and 158 that were inhibited by KRG in DEC KO mice, activated genes were involved in proliferation signaling, mineral absorption, and PPAR signaling whereas the inhibited genes were involved in arachidonic acid metabolism and peroxisomes. Our data indicate that inhibition of senescence-related Dec genes may explain the anti-aging efficacy of KRG.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.