• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
• /
• pp.101-101
• /
• 2000

MSC(Multispectral Camera), which will be a unique payload on KOMPSAT-II, is designed to collect panchromatic and multi-spectral imagery with a ground sample distance of 1m and a swath width of 15km at 685km altitude in sun-synchronous orbit. The instrument is designed to have an orbit operation duty cycle of 20% over the mission life time of 3 years. MSC electronics consists of three main subsystems; PMU(Payload Management Unit), CEU(Camera Electronics Unit) and PDTS(Payload Data Transmission Subsystem). PMU performs all the interface between spacecraft and MSC, and manages all the other subsystems by sending commands to them and receiving telemetry from them with software protocol through RS-422 interface. CEU controls FPA(Focal Plane Assembly) which contains TDI(Timc Delay Integration) CCD(Charge Coupled Device) and its clock drivers. PMU provides a Master Clock to synchronize panchromatic and multispectral camera. PDTS performs compression, storage and encryption of image data and transmits them to the ground station through x-band.

• 한국음향학회:학술대회논문집
• /
• 한국음향학회 1991년도 학술발표회 논문집
• /
• pp.163-168
• /
• 1991

In this paper, we propose a new systolic architecture for the order statistics(OS) constant false alarm rate(CFAR) processor. In the proposed architecture, each processing element(PE) can compare two reference data cells with one test cell simultaneously in each clock cycle. So the utilization of each PE in this architecture is 100% whereas the utilization of each PE in the systolic architecture previously reported by Ritcey and Hwang is 50% because of one clock delay between two adjacent PE's active in computation. This can speed up the data processing rate by a factor of two. With this architecture, we can obtain the reduced number of communication links between adjacent PE's and reduction of the latency by half in comparison with the one proposed by Ritcey and Hwang.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.809-810
• /
• 2006

An H.264 algorithm is commonly used for video compression applications. This algorithm requires a large number of data computations, for example, the sum of absolute difference (SAD) operation. We analyzed H.264 reference encoding workloads. The H.264 encoding program has 8.78% SAD operation. The SAD operation is to sum up 16 difference-values in H.264 $4{\times}4$ sub-blocks. In order to accelerate SAD operations, we implemented an application specific instruction-set processor (ASIP) that can execute SAD and data transfer instructions. The proposed coprocessor has an absolute value generator and a carry save adder (CSA) unit to sum up 8 difference-values per one clock cycle. We completed SAD operation in 2 clock cycles. Experimental results show that the performance is improved by 34% of total execution time.

• 한국통신학회논문지
• /
• 제27권3C호
• /
• pp.256-262
• /
• 2002

본 논문에서는 sign estimation technique (3)을 기초로 한 radix-4 모듈라 곱셈 알고리즘을 제안한다. Sign estimation technique은 carry와 sum의 형태로 표현되는 수에서 부호를 알아내는 것이다. 이 방법은 5비트 carry look-ahead adder로 구현이 가능하다. RSA와 같은 암호화 시스템에서는 모듈라 곱셈이 하드웨어의 성능을 좌우한다. 제안한 알고리즘은 modulus가 n 비트인 경우, 모듈라 곱셈 수행시 일반적인 알고리즘의 약 반 클럭 (n/2+3) 사이클만 필요하다. 그래서 매우 큰수의 modulus 사용하는 RSA 암호시스템에서 모듈라 멱승 연산에 매우 효율적이다. 또한 모듈라 곱셈의 하드웨어 성능을 향상하기 위해, CSA (Carry Save Adder)의 맨 마지막 출력에 사용되는 CPA (Carry Propagation Adder) 대신 고속 덧셈기(7)를 사용하였다. 모듈라 멱승 계산이 n 클럭이 소요되는 RL binary 방법을 적용하여 1024 비트 데이터를 RSA 암호화하는데 n(n/2+3) 클럭 사이클만 소요된다.

• 대한전자공학회논문지SD
• /
• 제47권5호
• /
• pp.1-9
• /
• 2010

이 논문에서는, 풀 HD 영상을 실시간에 처리가능한 새로운 화면 내 예측 및 DCTQ 하드웨어구조를 제안한다. 화면내 예측,.$4{\times}4$ 을 처리하기 위한 예측과 변환, 양자화, 역양자화, 역변환및 복원의 전체 cycle 을 줄일 수 있는 방법을 제안한다. $4{\times}4$ 예측 부호화 cycle을 줄이기 위해, 양자화과정을 예측 사이클에서 적용할 수 있도록 하였으며, 회로의 크기를 줄이기 위하여 9가지 모드 중 2개의 모드를 먼저 선택하는 알고리듬을 사용하였다. 또한 $16{\times}16$ 예측과 $8{\times}8$ 예측 과정를 하나의 코어를 이용하여 설계하므로 크기를 줄였다. 제안된 구조는 108Mhz 클럭에서 full HD영상을 30frame/sec에서 동작하며, 한 매크로블록의 처리 cycle 은 425 cycle이다.

• 전자공학회논문지C
• /
• 제34C권9호
• /
• pp.43-52
• /
• 1997

Processors using the superscalar rchitecture can achieve high performance by executing multipel instructions in a clock cycle. It is made possible by having multiple functional units and issuing multiple instructions to functional units simultaneously. But instructions can be dependent on one another and these dependencies prevent some instructions form being issued at the same cycle. In this paper, we designed an issue unit of a superscalar RISC microprocessor that can issue four instructions per cycle. The issue unit receives instructions form a prefetch unit, and issues them in order at a rate of as high as four instructions in one cycle for maximum utilization of functional units. By using an instruction buffer, the unit decouples instruction fetch and issue to improve instruction ussue rate. The issue unit is composed of an instruction buffer and an instruction decoder. The instruction buffer aligns and stores instructions from the prefetch unit, and sends the earliest four available isstructions to the instruction decoder. The instruction decoder decodes instructions, and issues them if they are free form data dependencies and necessary functional units and rgister file prots are available. The issue unit is described with behavioral level HDL (lhardware description language). The result of simulation using C programs shows that instruction issue rate is improved as the instruction buffer size increases, and 12-entry instruction buffer is found to be optimum considering performance and hardware cost of the instruction buffer.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅲ
• /
• pp.1685-1688
• /
• 2003

The modem multimedia applications which are video Processor, video conference or video phone and so forth require real time processing. Because of a large amount of image data, those require high compression performance. In this paper, the proposed image processing encoder was designed by using wavelet transform encoding. The proposed filter block can process image data on tile high speed because of composing individual function blocks by parallel and compute both highpass and lowpass coefficient in the same clock cycle. When image data is decomposed into multiresolution, the proposed scheme needs external memory and controller to save intermediate results and it can operate within 33㎒.

• 한국시뮬레이션학회논문지
• /
• 제3권2호
• /
• pp.15-25
• /
• 1994

Efficient event evaluation and propagation techniques are proposed to enhance the advancement of simulation clocks of conservative and optimistic logic simulation protocols on parallel processing environments. The first idea of the techniques proposed in this paper is to allow more than one event evaluation per simulation cycle and to pack more than one propagation event in a single message. The second idea is to use advancement windows resulted in good performance in parallelism and execution times.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
• /
• pp.164-167
• /
• 2000

This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제1권3호
• /
• pp.193-196
• /
• 2001

For wide locking range, an analog delay locked loop (DLL) was designed with the selective phase inversion scheme and the variable number of delay elements. The number of delay elements was determined adaptively depending on the clock cycle time. During the analog fine locking stage, a self-initializing 3-state phase detector was used to avoid the initial state problem associated with the conventional 3-state phase detector. With these schemes, the locking range of analog DLL was increased by four times compared to the conventional scheme according to the simulation results.