• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.3
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• pp.102-110
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• 2005

Piezoelectric transformers(PT) are expected to be small, thin and highly efficient, and which are attractive as a transformer with high power density for step down voltage. For these reasons, we have attempted to develop a step-down PT for the miniaturized adaptor. We propose a PT, operating in thickness extensional vibration mode for step-down voltage. This PT consists of a multi-layered construction in the thickness direction. In order to develop the step-down PT of 10 W class and turn ratio of 0.1 with high efficiency and miniaturization, the piezoelectric ceramics and PT designs are estimated with a variety of characteristics. The basic composition of piezoelectric ceramics consists of ternary yPb(Zr$_{x}$Ti$_{1-x}$)O$_{3}$-(1-y)Pb(Mn$_{1/3}$Nb1$_{1/3}$Sb$_{1/3}$)O$_{3}$. In the piezoelectric characteristics evaluations, at y=0.95 and x=0.505, the electromechanical coupling factor(K$_{p}$) is 58$\%$, piezoelectric strain constant(d$_{33}$) is 270 pC/N, mechanical quality factor(Qr$_{m}$) is 1520, permittivity($\varepsilon$/ 0) is 1500, and Curie temperature is 350 $^{\circ}C$. At y = 0.90 and x = 0.500, kp is 56$\%$, d33 is 250 pC/N, Q$_{m}$ is 1820, $\varepsilon$$_{33}$$^{T}$/$\varepsilon$$_{0}$ is 1120, and Curie temperature is 290 $^{\circ}C$. It shows the excellent properties at morphotropic phase boundary regions. PZT-PMNS ceramic may be available for high power piezoelectric devices such as PTs. The design of step-down PTs for adaptor proposes a multi-layer structure to overcome some structural defects of conventional PTs. In order to design PTs and analyze their performances, the finite element analysis and equivalent circuit analysis method are applied. The maximum peak of gain G as a first mode for thickness extensional vibration occurs near 0.85 MHz at load resistance of 10 .The peak of second mode at 1.7 MHz is 0.12 and the efficiency is 92$\%$.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.2
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• pp.150-158
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• 2010

The operational characteristics of a resonant DC/DC converter, which can harvest thermoelectric energy, is analyzed, depending on the relative magnitudes of the input voltage and the load voltage. The resonant converter consists of LC resonant circuit connected to DC input source and a resonant pulse converter in which the input energy is transferred to the load as the resonant capacitor voltage is peak. The resonant capacitor doubles the input voltage by the resonance phenomenon. By the relative magnitude between the input voltage and the output voltage, the resonant DC/DC converter operates in three different modes. For boost mode, the peak voltage of the resonant capacitor is smaller than the load voltage. For hybrid mode, the peak voltage of the resonant capacitor is bigger than the load voltage and every switching period has both the boost mode and the direct mode. For the direct mode, the input voltage is bigger than the load voltage and the converter transfers directly the input energy to the load without the switching operation. Operation principles and the feasibility of the converter for the thermoelectric energy harvesting are verified with PSPICE simulation and experiment.

• Journal of Internet of Things and Convergence
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• v.9 no.6
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• pp.93-98
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• 2023

In paddy rice farming, water management is a critical task. To suppress weed emergence during the early stages of growth, fields are deeply flooded, and after transplantation, the water level is reduced to promote rooting and stimulate stem generation. Later, water is drained to prevent the production of sterile tillers. The adequacy of water supply is influenced by various factors such as field location, irrigation channels, soil conditions, and weather, requiring farmers to frequently check water levels and control the ingress and egress of water. This effort increases if the fields are scattered in remote locations. Automated irrigation systems have been considered to reduce labor and improve productivity. However, the net income from rice production in 2022 was about KRW 320,000/10a on average, making it financially unfeasible to implement high-cost devices or construct new infrastructure. This study focused on developing an IoT-Based irrigation valve that can be easily integrated into existing agricultural infrastructure without additional construction. The research was carried out in three main areas: Firstly, an irrigation valve was designed for quick and easy installation on existing agricultural pipes. Secondly, a power circuit was developed to connect a low-power Cat M1 communication modem with an Arduino Nano board for remote operation. Thirdly, a cloud-based platform was used to set up a server and database environment and create a web interface that users can easily access.

• Membrane Journal
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• v.34 no.1
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• pp.58-69
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• 2024

Reverse electrodialysis (RED) is an electro-membrane process employing ion-exchange membranes (IEMs) that can harvest electric energy from the concentration difference between seawater and river water. Multivalent ions contained in seawater and river water bind strongly to the fixed charge groups of the IEM, causing high resistance and reducing open-circuit voltage and power density through uphill transport. In this study, a pore-filled anion-exchange membrane (PFAEM) with excellent monovalent ion selectivity and electrochemical properties was fabricated and characterized for RED application. The monovalent ion selectivity of the prepared membrane was 3.65, which was superior to a commercial membrane (ASE, Astom Corp.) with a selectivity of 1.27 under the same conditions. Additionally, the prepared membrane showed excellent electrochemical properties, including low electrical resistance compared to ASE. As a result of evaluating RED performance under seawater of 0.459 M NaCl/0.0510 M Na₂SO₄ and river water of 0.0153 M NaCl/0.0017 M Na₂SO₄, the maximum power density of 1.80 W/m² was obtained by applying the prepared membrane, which is a 40.6% improved output performance compared to the ASE membrane.

• Nuclear Engineering and Technology
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• v.56 no.3
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• pp.803-811
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• 2024

Nuclear accidents such as Fukushima Daiichi have highlighted the potential of passive safety systems to replace or complement active safety systems as part of the overall prevention and/or mitigation strategies. In addition, passive systems are key features of Small Modular Reactors (SMRs), for which they are becoming almost unavoidable and are part of the basic design of many reactors available in today's nuclear market. Nevertheless, their potential to significantly increase the safety of nuclear power plants still needs to be strengthened, in particular the ability of computer codes to determine their performance and reliability in industrial applications and support the safety demonstration. The PASTELS project (September 2020-February 2024), funded by the European Commission "Euratom H2020" programme, is devoted to the study of passive systems relying on natural circulation. The project focuses on two types, namely the SAfety COndenser (SACO) for the evacuation of the core residual power and the Containment Wall Condenser (CWC) for the reduction of heat and pressure in the containment vessel in case of accident. A specific design for each of these systems is being investigated in the project. Firstly, a straight vertical pool type of SACO has been implemented on the Framatome's PKL loop at Erlangen. It represents a tube bundle type heat exchanger that transfers heat from the secondary circuit to the water pool in which it is immersed by condensing the vapour generated in the steam generator. Secondly, the project relies on the CWC installed on the PASI test loop at LUT University in Finland. This facility reproduces the thermal-hydraulic behaviour of a Passive Containment Cooling System (PCCS) mainly composed of a CWC, a heat exchanger in the containment vessel connected to a water tank at atmospheric pressure outside the vessel which represents the ultimate heat sink. Several activities are carried out within the framework of the project. Different tests are conducted on these integral test facilities to produce new and relevant experimental data allowing to better characterize the physical behaviours and the performances of these systems for various thermo-hydraulic conditions. These test programmes are simulated by different codes acting at different scales, mainly system and CFD codes. New "system/CFD" coupling approaches are also considered to evaluate their potential to benefit both from the accuracy of CFD in regions where local 3D effects are dominant and system codes whose computational speed, robustness and general level of physical validation are particularly appreciated in industrial studies. In parallel, the project includes the study of single and two-phase natural circulation loops through a bibliographical study and the simulations of the PERSEO and HERO-2 experimental facilities. After a synthetic presentation of the project and its objectives, this article provides the reader with findings related to the physical analysis of the test results obtained on the PKL and PASI installations as well an overall evaluation of the capability of the different numerical tools to simulate passive systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.25-33
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• 2007

In this paper, the high isolation and wideband 94 GHz MIMIC(Millimeter-wave Monolithic Integrated Circuit) single balanced cascode mixer was designed and fabricated. Also, we designed and fabricated a 3 dB tandem coupler which has a high isolation and wideband characteristic. The single balanced resistive mixer which does not require an external IF balun was designed using the 0.1 ${\mu}m$ InGaAs/InAlAs/GaAs metamorphic HEMT(High Electron Mobility Transistor). The DC characteristics of MHEMT's are 665 mA/mm of drain current density, 691 mS/mm of maximum transconductance. The current gain cut-off frequency($f_T$) is 189 GHz and the maximum oscillation frequency($f_{max}$) is 334 GHz. A 94 GHz single balanced cascode mixer was fabricated using our 0.1 ${\mu}m$ MHEMT MIMIC process. From the measurements, the fabricated couplers showed wideband characteristics. The conversion loss of single balanced cascode mixer was 9.8 dB at an LO power of 10.9 dBm. The LO to RF isolation of single balanced cascode mixer was 29.5 dB at 94 GHz. We obtained in this study a higher LO-RF isolation compared to some other single balanced mixers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2395-2402
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• 2013

An active-RC channel selection filter (CSF) with the bandwidth of 40MHz and the improved linearity is proposed in this paper. The proposed CSF is the fifth butterworth filter which consists of a first order low pass filter, two second order low pass filters of a biquad architecture, and DC feedback circuit for cancellation of DC offset. To improve the linearity of the CSF, a body node of a MOSFET for a switch is connected to its source node. The bandwidth of the designed CSF is selected to be 10MHz, 20MHz and 40MHz and its voltage gain is controlled by 6 dB from 0 dB to 24 dB. The proposed CSF is designed by using 40nm 1-poly 8-metal CMOS process with a 1.2V. When the designed CSF operates at the bandwidth of 40 MHz and voltage gain of 0 dB, the simulation results of OIP3, in-band ripple, and IRN are 31.33dBm, 1.046dB, and 39.81nV/sqrt(Hz), respectively. The power consumption and layout area are $450{\times}210{\mu}m^2$ and 6.71mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2273-2280
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• 2013

This article introduces the next-generation air surveillance system and investigates how to design of front-end low noise amplifier of the ground station receiver. In consideration of the international standard documentation and the performance of existing products, the study conducts the link budget on the entire system so that it can be competitive in terms of receive sensitivity or reliability. To obtain a proper low noise amplifier, standards of design are decided so that such factors as gain, gain flatness, and reflective loss can be optimal. In its design, the bias circuit appropriate for the characteristics of low power, low noise, or high gain was built, and according to the results of the simulation conducted after the optimal design, its gain was 16.24dB, noise factor was 0.36dB, input-output reflective loss was -18dB and -28dB each, and frequency stability was 1.11. According to the results measured after the design, its gain was 17dB, noise factor was 0.51dB, gain flatness was 0.23dB, and input-output reflective loss was -18.28dB and -24.50dB each, so the results gained were suitable for building the overall system.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.