• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.38-44
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• 2007

This paper describes a 12 bit 80MHz CMOS D/A converter for wireless transceiver. Proposed circuit in the paper employes segmented structure which consists of four stage 3bit thermometer decoders. Proposed D/A converter is manufactured 0.35um CMOS n-well digital standard process and measurement results show a ${\pm}1.36SB/{\pm}0.62LSB$ of INL/DNL and $46pV{\cdot}s$ of glitch energy. SNR and SFDR are measured to be 58.5dB and 64.97dB @ Fs=80MHz and Fin=19MHz with a total power consumption of 99mW. Such results proved that our work has low power consumption, high linearity, low glitch and improved dynamic performance. Therefore, our work can be appled to various high speed and high performance circuits.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.7
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• pp.914-919
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• 2004

When the motor is rotating, the torque and rpm are varying as the loads or the driving status connecting through reduction units are changing. On the contrary, one can monitor the changes of the loads or the driving status in the manner of measuring motor torque and rpm. There is a torque measuring method using the strain gauge and bridge circuit. But, because this is the contact method, it has the life time which is dependent on rotating velocity and used time. So this system demands on replacement of some Parts or whole system itself for maintenance. And this system is also relatively big and expensive, requiring preceding annoying process. In this paper, we are going to suppose non-contact method to measure torque and rpm using the Hall effects sensor For this we have made the planetary geared reduction motor with Hall sensors and with the monitoring system. The monitoring system displays the sensing data(torque, rpm) and calculated data( power) and also has the network capability with Bluetooth protocol. Our solution is much more inexpensive ;md simple method to measure torque and rpm than before.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

• Fire Science and Engineering
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• v.24 no.6
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• pp.61-68
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• 2010

In this paper, a research and development result for the implementation of single station fixed temperature detector for residential fire prevention is described. The detector was developed for the certification in Japanese market because of very low domestic market situation. It is in the situation that there is no other regulation especially for residential detectors in Korea, Japanese case has been reviewed. Investigation of domestic legal circumstances and a comparative study for the test standard owned by KFI (Korea Institute of Fire Industry & Technology) and JFEII (Japan Fire Equipment Inspection Institute) respectively are also indicated. The detector alarms with a buzzer and an indicating LED. In the implementation ultra low power MCU(Micro Controller Unit) is applied to control the sleeping state and the monitoring state properly with low current consumption. To sense the temperature fast response thermistor is adopted in the design of fixed temperature residential detector. Automatic test function and alarm stop function are also considered in the design. The major factors which influence to current consumption are explained for the purpose of design reference. Main electronics circuit parts related to it's characteristics of the detector are described. It is explained that the measured current and experimental result of the battery discharge can be met over 10 years operation.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.7
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• pp.665-671
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• 2017

The alkali-Metal Thermal-to-electric Converter (AMTEC) is one of the promising static energy conversion technologies for the direct conversion of thermal energy to electrical energy. The advantages over a conventional energy converter are its high theoretical conversion efficiency of 40% and power density of 500 W/kg. The working principle of an AMTEC battery is the electrochemical reaction of the sodium through an ion conducting electrolyte. Sodium ion pass through the hot side of the beta"-alumina solid electrolyte (BASE) primarily as a result of the pressure difference. This pressure difference across the BASE has a significant effect on the overall performance of the AMTEC system. In order to build the high pressure difference across the BASE, hermeticity is required for each joined components for high temperature range of $900^{\circ}C$. The AMTEC battery was manufactured by utilizing robust joining technology of BASE/insulator/metal flange interfaces of the system for both structural and electrical stability. The electrical potential difference between the anode and cathode sides, where the electrons emitted from sodium ionization and recombined into sodium, was characterized as the open-circuit voltage. The efforts of technological improvement were concentrated on a high-power output and conversion efficiency. This paper discusses about the joining and performance of the AMTEC systems.

• Journal of Korean Society of Disaster and Security
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• v.10 no.1
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• pp.85-90
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• 2017

The purpose of this study is to investigate the effect of vertical and horizontal refraction on the lower part of the power supply and control system of various facilities and machinery that use electricity, so that the power distribution system, which is an important electric facility installed in buildings and public facilities, Type earthquake resistant pads to protect the substructure and prevent short-circuiting on the upper part of the system. The GR-63-CORE (Scale 8.3 class) It is earthquake disaster prevention and disaster prevention technology that satisfies seismic performance. As a research result, it is possible to protect the electricity and communication infrastructure, which can contribute to shortening the time for recovering the electric facilities to the normal state in case of an earthquake, and preventing the fire caused by the destruction of the electricity supply facility in case of an earthquake. As a result, it is possible to minimize the spread of fire that occurs when a large-scale earthquake occurs and to minimize the damage of people and damage to property, and it can contribute to the securing of electric infrastructure that enables citizens to quickly recover to daily life even after suffering a major earthquake. In addition, the technology can be applied to ensure the seismic resistance of the equipment in the communication and computer room, and it can be applied to various fields where the facility function can be stopped due to the shaking of the earthquake base.

• Journal of the Korean Society of Marine Environment & Safety
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• v.21 no.6
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• pp.759-769
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• 2015

Diode rectifiers are very popular in industry. However, they include large low-order harmonics in the input current and do not satisfy harmonic current content restrictions. To reduce the harmonics to the power system, several methods have been introduced. It is heavy and expensive solution to use passive filters as the solution for high power application. Another solution for the harmonic filter is utilization of active filter, but it is too expensive solution. Diode rectifiers with configurations using switching device have been introduced, but they are very complicated. The combined 12-pulse diode rectifier with the square auxiliary voltage supply has been introduced. It has the advantages that auxiliary circuit is simple and inexpensive compared to other strategies. The advanced auxiliary voltage supply in this thesis is presented as a new solution. When the square auxiliary voltage supply applied, the improvement of THD is 6~60[%] in whole load range. But when the advanced auxiliary voltage supply applied, it shows stable and excellent reduction effect of THD as 57~71[%]. Especially, for the case with 10[%] load factor, reduction effect of THD has little effect as 6[%] in the case of inserting a square auxiliary voltage supply. But when the proposed new solution applied, reduction effect has excellent effect as 71[%]. Theoretical analysis of the combined 12-pulse diode rectifier with the advanced auxiliary voltage supply is presented and control methods of the auxiliary supply is proposed. The reduction in the input current harmonics is verified by simulation using software PSIM.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.170-175
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• 2016

In order to transmit baseband signals through frequency dividing devices, we studied the transfer function of the device in the term of the baseband signal distortion. From the analysis, it is shown that the magnitude of the envelope signal is related to the mixer gain and the insertion loss of the low pass filter whilst the phase is the additional function with the 1/2 of the phase delay. For the purpose of the verification of the study, we designed a dynamic frequency divider at 1,400 MHz. The operating frequency range of the device is closely related to the conversion gain of mixers and the amplitude of input signal, and becomes wide as the conversion gain of mixers increases. The designed frequency divider operates between 0.9 GHz and 3.2 GHz, for -14.5 dBm input power. The circuit shows 20 mW power dissipation at $V_{DD}=2.5V$, and the simulation result shows that an amplitude modulated signal at 1,400 MHz with the modulation index of 0.9 was successfully downconverted to 700 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.13-22
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• 2001

This paper presents three dimensional structure of RF packages and the improvement effect of its electrical characteristics when implementing RF transceivers. We divided RF modules into several subunits following each subunit function based on the partitioning algorithm which suggests a method of three dimension stacking interconnection, PAA(pad area array) interconnection and stacking of three dimensional RF package structures. 224MHz ITS(Intelligent Transportation System) RF module subdivided into subunits of functional blocks of a receiver(RX), a transmitter(TX), a phase locked loop(PLL) and power(PWR) unit, simultaneously meeting the requirements of impedance characteristic and system stability. Each sub­functional unit has its own frequency region of 224MHz, 21.4MHz, and 450KHz~DC. The signal gain of receiver and transmitter unit showed 18.9㏈, 23.9㏈. PLL and PWR modules also provided stable phase locking, constant voltages which agree with design specifications and maximize their characteristics. The RF module of three dimension stacking structure showed $48cm^3$, 76.9％ reduction in volume and 4.8cm, 28.4％ in net length, 41.8$^{\circ}C$, 37% in maximum operating temperature, respectively. We have found that three dimensional PAA package structure is able to produce high speed, high density, low power characteristics and to improve its functional characteristics by subdividing RF modules according to the subunit function and the operating frequency, and the features of physical volume, electrical characteristics, and thermal conditions compared to two dimensional RF circuit modules.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.