• Journal of the Korean Society of Marine Environment & Safety
• /
• v.29 no.2
• /
• pp.223-229
• /
• 2023

Seawater batteries are next-generation secondary batteries that use seawater as a cathode. They utilize marine resources to provide competitive prices, high eco-friendliness, and a structure suitable for marine applications. Based on these advantages, pouch types and prismatic types have been studied and developed assuming natural seawater exposure. However, because of the electrical characteristics of the secondary battery, its capacity and internal resistance vary depending on the use environment. These characteristics are not only utilized for predicting the life of a battery but also have a direct effect on the capacity and power suitable for a specific situation. Therefore, the internal resistance was analyzed in this study by measuring the capacity depending on the seawater battery use environment and the state-of-charge-open-circuit-voltage measurement method.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.7 no.10
• /
• pp.895-903
• /
• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• 2022.06a
• /
• pp.339-343
• /
• 2022

In this study, a method for simplifying the structure of the VDES RF receiver, and the gain control method of the receiver to comply with the international standard in this structure was described. The input level of the wanted signal and unwanted signal to the receiver was defined, and when the two signals were input, the saturation state at the ADC was checked at the receiver output. As a result of the simulation by the circuit simulator, it was satisfied that the output power of the receiver was in the SFDR region of ADC with respect to the adjacent channel interference ratio, intermodulation, and blocking level. Through this study, it was found that the structure of th proposed RF receiver conforms to the international standard.

• Journal of Aerospace System Engineering
• /
• v.17 no.5
• /
• pp.42-57
• /
• 2023

In this paper, to increase the research capability of flight missions and maintenance in operating military aircraft, we studied the requirements for additional mounting of flight video and data recorders and safety verification methods. The verification process of the recorder equipment itself, structural safety in the aircraft system, power and electrical safety, electromagnetic compatibility, and impact of airworthiness are described in accordance with military standards and operating environment requirements. In addition, through ground/flight tests, the results of functional operation suitable for the influence and demand of interference between the flight video and data recorder and other systems are also presented.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.16 no.6
• /
• pp.465-471
• /
• 2023

This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

• Journal of the Korean Applied Science and Technology
• /
• v.40 no.4
• /
• pp.786-796
• /
• 2023

The purpose of this study was to examine the influencing factors of perceived safety for CCTV(Closed Circuit Television), and to confirm the correlation between fear of crime, social disorder, physical disorder in the community, and perceived safety for CCTV. Subjects were 140 students from one college located in H city using survey from June 17, 2022 to August 25, 2022. Data was analyzed by descriptive statistics, Pearson's correlation, and Stepwise multiple regression using the SPSS 23.0 program. As a result of the study, fear of crime was correlated with social disorder, physical disorder among community characteristics, and perceived safety of CCTV. Also, social disorder among community characteristics was correlated with physical disorder, perceived safety of CCTV, and physical disorder was correlated with perceived safety of CCTV. The factors affecting perceived safety for CCTV were fear of crime and social disorder, and the explanatory power was 57.2%(Adjusted R²=.572). In conclusion, it is necessary to improve the perceived safety of CCTV by improving the awareness of fear of crime and social disorder.

• Journal of IKEEE
• /
• v.28 no.1
• /
• pp.33-37
• /
• 2024

In this paper, we report the design and the measurement of a X-band low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) using a 0.25 ㎛ gate length microstrip GaN-on-SiC high electron mobility transistor (HEMT) technology. The developed X-band GaN-based LNA MMIC achieves small signal gain of 22.75 dB ~ 25.14 dB and noise figure of 1.84 dB ~ 1.94 dB in the desired band of 9 GHz to 10 GHz. Input and output return loss values are -11.36 dB ~ -24.49 dB and -11.11 dB ~ -17.68 dB, respectively. The LNA MMIC can withstand 40 dBm (10 W) input power without performance degradation. The chip dimensions are 3.67 mm × 1.15 mm. The developed GaN-based LNA MMIC is applicable to various X-band applications.

• Transactions on Semiconductor Engineering
• /
• v.2 no.3
• /
• pp.1-5
• /
• 2024

This paper presents a crystal-less reference clock recovery (CR) frequency synthesizer with compensation designed for Bluetooth Low Energy (BLE) Smart-tag applications, operating at frequencies of 32, 72, and 80MHz. In contrast to conventional frequency synthesizers, the proposed design eliminates the need for external components. Using a single-ended antenna to receive a minimal input power of -36dBm at a 2.4GHz signal, the CR synthesizes frequencies by processing the RF signal received through a Low Noise Amplifier ( L N A ) . This approach allows the system to generate a reference clock without relying on a crystal. The received signal is amplified by the LNA and then input to a 16-bit ACC (Automatic Clock Compensation) circuit. The ACC compares the frequency of the received signal with the oscillator output signal, using the synthesis of a 32MHz reference clock through a frequency compensation method. The oscillator is constructed using a Ring Oscillator (RO) with a Frequency Divider, offering three different frequencies (32/72/80MHz) for various system components. The proposed frequency synthesizer is implemented using a 55-nm CMOS process.

• Korean Journal of Materials Research
• /
• v.3 no.6
• /
• pp.614-623
• /
• 1993

Electrical characteristics of LiF-$Li_{2}O-B_{2}O_{3}-P_{2}O_5$ glasses with fixed $Li_2O$ content have been investigated by using AC impedance spectroscopy. Part of the total lithium ions present in these glasses contributes to conduction, and the changes in electrical conductivity with composition was inconsistent with the weak electrolyte model. The power law could not be used to determine the hopping ion concentration in these glasses. Both mobile carrier density and mobility have been modified as Li were added in the form of LiF. The formation of $(B-O-P)^-,di^-$, and metaborate group gave additional available sites for Li+ diffusion causing the enhancement of conductivity. The observed maximum conductivity was $2.43 \times 10^{-4}$S/cm at $150^{\circ}C$ at the composition containing 8mol% LiF. The decomposion potential amounted to 5.94V. The Li/glass electrolyte/$TiS_2$ solid-state cell showed open circuit voltage of 3.14V and energy density of 22 Wh/Kg at $150^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.8
• /
• pp.22-26
• /
• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.