• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.46-56
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• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.500-505
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• 2002

In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed frequency divider has designed in a standard 0.25$\mu\textrm{m}$ CMOS technology. To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65$\mu\textrm{m}$ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz, a tuning range of ${\pm}$10%, and a gain of 154MHz/V. The simulated frequency synthesizer performance has a settling time of 1.5${\mu}\textrm{s}$, a frequency range from 820MHz to 1GHz and power consumption of 70mW at 2.5V power supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.24-30
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• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.537-540
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• 1992

This paper presents Samsung CNC (Computer Numerical Controller) system with an intel 80486/487 as the main CPU and a 32 bit floating point DSP(Digital Signal Processor) TMS320C30 as the motion control CPU. The Samsung CNC system diverse user-frienly characteristics such as multi-tasking, powerful menu system, internal PLC system, and 2/3 dimensional graphics in wire and solid mode. The main CPU executes central processing program, user interface program, interpreter, BMI, etc while the motion control CPU carries out some interpolations, acceleration/deceleration, and PID control algorithm with feedforward terms. Complex interpolations except linear and circular ones are performed on the main control CPU. The experimental results for the circular interpolation under linear acceleration/deceleration shows that the proposed CNC system can be widely used in controlling machining centers with good machining accuracy.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.115-122
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• 1997

In this paper, on-chp atomatic tuning circuit, using proposed integration level approximation technique, is designed to tuning of the variation of RC time-constant due to aging or temperature variation, etc. This circuit reduces the error, the difference between code values and real outputs of integrator, which is drawback of presented dual-slope tuning circuit and eliminates modulations of processing signals in integrated circuit due to fixed tuning codes during ordinary operation. This system is made up of simple integrator, A/D converter and digital control circuit and all capacitors are replaced by programed capacitor arrays in this system. This tuning circuit with 4 bit resolution achieves $-9.74{\sim}+9.68%$ of RC time constant error for 50% resistance variation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.67-71
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• 2011

Existing face detection systems, which are used for digital door locks, digital cameras, video surveillance systems, and so on, are software-based implementation for relatively low level resolution images. Therefore, in this case, there are difficulties in detecting faces in a real-time fashion due to the increasing amount of operational processing as well as in allowing the requirements of face detections for HD(High Definition) resolutions. A hardware approach is necessary to efficiently find faces for HD images in real-time embedded systems. This paper proposes and implements a hardware architecture for an LBP(Local Binary Pattern) operation which is a time-consuming part as one of preprocessing steps for face detection. The hardware architecture proposed in this research has been implemented and tested with a FPGA(Field Programmable Gate Array) chip, and shown that the approach guarantees efficient face detection for HD images.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.99-102
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• 2012

An image scaler is a IP used in a image processing block of display devices to adjust image size. Proposed image scaler adopts line memories instead of a conventional method using a frame memory. This method reduced hardware resources and enhanced data precision by using shift operations that number is multiplied by $2^m$ and divided again at final stage for scaling. Also image scaler increased efficiency of IP by using serial divider to calculate parameters by itself. Parameters used in image scaling is automatically produced by it. Suggested methods are designed by Verilog HDL and implemented with Xilinx Vertex-4 XC4LX80 and ASIC using TSMC 0.18um process.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.324-332
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• 2005

In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

• Korean Journal of Food Science and Technology
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• v.19 no.2
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• pp.129-133
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• 1987

To develop a microcomputer-based data acquisition system for measurement of variables such as temperature and weight in food process, a low-cost data acquisition system was developed using an Apple II microcomputer. The system consisted of a microcomputer, a temperature sensor made of pt-100, a strain gauge load cell for weighing, a preamplifier for signal conditionings and an interface device. Interface device was built with programmable interface chip MC 6821, tristate buffer 74244 and analog-to-digital converter ADC 0809. The analog signals of temperature and weight were serially acquisited upon the program. The BASIC language was used for operating the data acquisition and data handling programs. The system successfully measured the variables such as temperature and weight with various sampling intervals in food dehydration process.

• Transactions of Materials Processing
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• v.17 no.8
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• pp.594-599
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• 2008

This paper presents a micro air pump based on the synthetic jet to supply reactant at the cathode side for micro fuel cells. The synthetic jet is a zero mass flux device that converts electrical energy into the momentum. The synthetic jet actuation is usually generated by a traditional PZT-driven actuator, which consists of a small cylindrical cavity, orifices and PZT diaphragms. Therefore, it is very important that the design parameters are optimized because of the simple configuration. To design the synthetic jet micro air pump, a numerical analysis has been conducted for flow characteristics with respect to various geometries. From results of numerical analysis, the micro air pump has been fabricated by the PDMS replication process. The most important design factors of the micro air pump in micro fuel cells are the small size and low power consumption. To satisfy the design targets, we used SP4423 micro chip that is high voltage output DC-AC converter to control the PZT. The SP4423 micro chips can operate from $2.2{\sim}6V$ power supply(or battery) and is capable of supplying up to 200V signals. So it is possible to make small size controller and low power consumption under 0.1W. The size of micro air pump was $16{\times}13{\times}3mm^3$ and the performance test was conducted. With a voltage of 3V at 800Hz, the air pump's flow rate was 2.4cc/min and its power consumption was only 0.15W.