• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.771-782
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• 2000

In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of theH.263 video codec is implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resolution block matching algorithm using multiple candidates and spatial correlation in motion vector fields (MRMCS), is suggested to reduce the chip size. Software optimization techniques are also explored by using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD)obtained from the motion estimator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.103-108
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• 2014

The flash memory which is exploited on hand-held devices such as smart phones is a non-volatile storage and has the benefit that it can store mass data at a small sized chip. To process queries on the mass data stored in the flash memory, the index scheme should be exploited. However, since the write operation of the flash memory is slower than the read operation and the overwrite is not supported, it is required to reevaluate the performance of the index and find out the drawbacks. In this paper, we evaluate the performance of a space division typed index scheme on the flash memory. To do this, we implement the fixed grid file and measure the average speeds of the query and update processing on a various condition and compare the value of the flash memory with that of the magnetic disk.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.111-116
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• 2003

In this paper, a CMOS baseband analog receiver for wireless home network is discussed. It is composed of a Gilbert type mixer, an Elliptic 6th order 1ow pass filter, and a 6-bit A/D converter. The main role of the mixer is generating a mixed analog signal between the 200MHz output signal of CMOS RF stage and the 199MHz local oscillator. After the undesired high frequency component of the mixed signal comes out. Finally, the analog signal is converted into digital code at the 6-bit A/D converter, The proposed receiver is fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly 5-metal CMOS technology, and the chip area is 200${\mu}{\textrm}{m}$ X1400${\mu}{\textrm}{m}$. the receiver consumes 130㎽ at 2.5V power supply.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.12 no.6
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• pp.78-86
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• 2013

In this paper, we propose design of a high-performance vehicle imaging information system for an efficient vehicle imaging stabilization. The proposed system was designed the algorithm by divided as motion estimation and motion compensation. The motion estimation were configured as local motion vector estimation and irregular local motion vector detection, global motion vector estimation. The motion compensation was corrected for the four directions for compensate to the shake of vehicle video image using estimate GMV. The designed algorithm were designed the motion compensation technology chip by applied to IP for vehicle imaging stabilization. In this paper, the experimental results of the proposed vehicle imaging information system were proved to the effectiveness by compared with other methods, because imaging stabilization of moving vehicle was not used of memory by processing real-time. Also, it could be obtained to reduction effect of calculation time by arithmetic operation through to block matching.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.3
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• pp.111-117
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• 2018

Heterogeneous multi-core environment integrated with different functional cores is the powerful tool for the embedded system that became more complex and diverse. Specialized application requires one chip solution with different operating system over different cores. But this heterogeneity causes difficult configuration of the development environment, makes hard to develop and test software. We show the environment of heterogeneous multi-core processing can be mapped to symmetric multi-core environment. We construct Linux based RPMsg for the data exchange between processes similar with the heterogeneous multi-core RPMsg and experiment that the proposed environment can be used to reduce the steps of the heterogeneous multi-core application development. With this simplification, we suggest simulation method for easy development and debugging the heterogeneous multicore environment that makes complex steps to simple.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.2 s.314
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• pp.74-81
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• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of H.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation and in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA(Field Programmable Gate Array) implementation results for the proposed structure show 39% and 32% gate count reduction in comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

• Journal of Sensor Science and Technology
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• v.20 no.5
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• pp.357-362
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• 2011

This paper demonstrates a novel electrodynamic technique to remove particles from the wall of microchannels. Dielectrohporesis(DEP) is generated by applying alternating electric potentials to the interdigitated electrodes integrated at the bottom of the micro-channel. The proposed technique is applied to a general microfluidic channel as a feasibility test. To examine the wall loss reduction efficiency, 10 ${\mu}m$ diameter Polystyrene latexes(PSL) were supplied to the inlet of the device. Then, the concentration of collected particles through devices was measured. In the experiment for 10 ${\mu}m$ diameter PSL particles, the concentration of the injected particles was $174.25{\times}10^4$ particles/ml. However, the concentration of collected particles at the outlet was $52.25{\times}10^4$ particles/ml. Only 30 % of particles had arrived at the outlet and 70 % of particles had adhered to the wall of the microfluidic channel. By applying alternating electric potentials from 0 to 20 $V_{pp}$ at 3 MHz, the concentration of injected particles was 135.00${\times}10^4$ particles/ml, the concentration of collected particles was increased as $105.25{\times}10^4$ particles/ml at 20 $V_{pp}$ at the outlet. When the electric potential was 20 $V_{pp}$, the particle loss was decreased by 39 % (initial loss: 70 %, loss at 20 Vpp: 31 %) with 10 ${\mu}m$ particle. The particle loss was decreased along to the incensement of electric potentials and the enlargement of the diameter of particles. According to these measured results, it was confirmed that the proposal of using DEP technique could be a good candidate for particle loss reduction in micro-particle processing chip application. Moreover, it is expected that the proposed technique could enhance performance of microfluidic and biochip devices.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.211-214
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• 2003

Current VOD embodiment way is embodied using PC base. However, achieved research that embody this by Embedded System that PC base is not. OS of this system used WindowsCE.net and x86core used having built-ined SC1200(National company's Geode's familys) by CPU and memory used 128MByte SDRAM. Used Mpeg Decoder for processing of video data, and used Enthernet Controller for Internet. Composite, component, S-Video of video output section of this system is and select one of these and connect on TV and did so that get into action. Actuality implementation manufactured necessary BIOS, WinodwsCE.NET Porting, DeviceDriver in system development and necessary simple Application in action confirmation, and Video Player used Window Media Player had included to WindowsCE.net. Therefore, treatise that see to supplement shortcomings of VOD service been embodying in current PC in Embedded System's form embody that there is sense do can.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.259-268
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• 2008

Multi-Core processors have become main-stream microprocessors in recent years. Servers based on these multi-core processors are widely adopted in High Performance Computing (HPC) and commercial business applications as well. These servers provide increased level of parallelism, thus can potentially boost the performance for applications. However, the shared resources among multiple cores on the same chip can become hot spots and act as performance bottlenecks. Therefore it is essential to optimize the use of shared resources for high performance and scalability for the multi-core servers. In this paper, we conduct experimental studies to analyze the positive and negative effects of the resource sharing on the performance of HPC applications. Through the analyses we also characterize the performance of multi-core servers.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.463-467
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• 2000

In this paper, we have implemented the Web Server Patient Monitoring System using PPP. It is composed of two parts. The first part is the Analog board for acquiring ECG signals. The second part is the module for processing and transmitting the acquired signal. The second part is using PPP for dial-up networking, TCP/IP for Internet, HTTP for web browser and JAVA program for a Patient Monitoring Program in one chip. In home, it is not need to establish another network line because it uses a telephone line. And a user who want to monitor a patient's biosignal can monitor a patient without wholly open network because it is the network sewer. The Patient Monitoring Program runs on a web browser by downloaded JAVA codes when a user connect to this system. It can make the Home Patient Monitoring Program decrease cost. It can help to avoid the limitation of monitoring a patient.