• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.10-17
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• 2012

This paper presents a clock regenerator using two $2^{nd}$ order ${\sum}-{\Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${\sum}-{\Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${\mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.7
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• pp.28-37
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• 1997

In this paper, we designed a motion estimator for MPEG-2 video coder using VHDL. Motion estimation is indispensable for encoding MPEG 2 video. Motion estimation takes over 50% computation power of video encoding 37 frames per second and is suitable for real-time processing. The number of data accesses for computation is fewer than 2 times compared with that of old one. This makes slower memory module available. We minimize input pins to migrate input data through PEs. This processor can compute various motio estimation modes at one calculation that is supported by MPEG-2 video standard. Also independent control architecture makes this processor a single processor or a sub module in amultimedia chip.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.274-277
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• 1999

The paper describes a implementation of space vector pulse-width modulation (SVPWM) voltage source inverter using Field Programmable Gate Array(FPGA) for a induction motor control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QL16X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed FPGA for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance voltage source inverter drives. Simulation and Implementation results are shown to verify the usefulness of FPGA as a Application Specific Integrated Circuit(ASIC) in power electronics applications

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.12
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• pp.804-810
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• 2004

There are two important things for the general purpose neural network processor. The first is a capability to build various structures of neural network, and the second is to be able to support suitable learning method for that neural network. Some way to process various learning algorithms is required for on-chip learning, because the more neural network types are to be handled, the more learning methods need to be built into. In this paper, an improved hardware structure is proposed to compute various kinds of learning algorithms flexibly. The hardware structure is based on the existing modular neural network structure. It doesn't need to add a new circuit or a new program for the learning process. It is shown that rearrangements of the existing processing elements can produce several neural network learning modules. The performance and utilization of this module are analyzed by comparing with other neural network chips.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.111.5-111
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• 2001

This paper places great importance on performance improvement of Galvanometer system used for laser display, laser processing, marking system. Fundamentally, we implement control system, on that assumption that laser source exists, and design basic PID controller. Hardware is composed of DSP(TMS320C32) chip, and the position compensation of Galvanometer is performed by using 16-bit A/D and D/A converter. Through frequency response analysis and simulation, the attribute of plant and controller is captured and then, total system is analyzed. We deliberate noise problem that can be caused from analog signal as driving signal for Galvanometer.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.102.2-102
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• 2001

In this study, a solid-state laser system adopting a new real time multi-discharge (RTMD) method in which three flashlamps are turned on consecutively was designed and fabricated to examine the pulse width and the pulse shape of the laser beams depending upon the changes in the lamp turn-on time. That is, this study shows a technology that makes it possible to make various pulse shapes by turning on three flashlamps consecutively on a real-time basis with the aid of a PIC one-chip microprocessor, With this technique, the lamp turn-on delay time can be varied more diversely from 0 to 10 ms and the real-time control is possible with an external keyboard, enabling various pulse shapes. In addition, longer pulses can be more widely used for industrial processing and lots of medical purposes.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.97.6-97
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• 2002

In this paper, we present an arrayed flexible tactile sensor, which can detect contact normal forces as well as positions. The tactile sensor is developed using Polyvinylidene Fluoride (PVDF) that is known as piezoelectric polymer, and the surface electrode is fabricated using silk-screening technique with silver. We develop a charge amplifier in order to amplify the small signal from the sensor, and a fast signal processing unit by using a DSP chip. The developed tactile sensor is physically flexible and it can be deformed three-dimensionally to any shape so that it can be placed on anywhere on the curved surface. In the future, the developed sensor is applied to a dexterous robotic hand...$\textbullet$ Tactile sensing, PVDF, Robot hand

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.864-867
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• 2002

Introduction of digital communication network such as Integrated Services Digital Networks(ISDN) and digital storage media have rapidly developed. Due to a large amount of image data, compression is the key techniques in still image and video using digital signal processing for transmitting and storing. Digital image compression provides solutions for various image applications that represent digital image requiring a large amount of data. in this paper, the proposed DWT(Discrete Wavelet Transform) filter bank is consisted of simple architecture, but it is efficiently designed that a user obtains a wanted compression rate as only input parameter. If it is implemented by FPGA chip, the designed encoder operates in 12MHz.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.940-943
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• 2002

This paper presents hardware implementations of the two representative cryptographic algorithms, Advanced Encryption Standard (Rijndael), and the present American federal standard (Triple DES) using a PCI- based FPGA board named "EBSW-1" This board bases on a FPGA chip (Xilinx Virtex300 XCV300PQ240-4). The implementation results of these two algorithms were tested successfully. AES circuit could proceed an encryption as well as a decryption two times faster than the Triple-DES circuit, while the former circuit used higher rates of CLBs. Besides, if these architectures use pipeline-registers, the processing speed will be increased about 1.5 times than the presented circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.1-13
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• 1995

In this paper, a specification for wireless LAN MODEM using direct sequence spread spectrum (DS/SS) technique is presented. Some algorithms and hardware architectures for an efficient implementation of the DS/SS MODEM are suggested. In the method, all baseband signal processing are done digitally for single chip implementation. Schemes of DQPSK baseband modulation/demodulation, despreading with digital matched filter, digital timing recovery, and efficient carrier sensing are among the discussed algorithms. We also performed various kinds of simulations to evaluate the system performance and to extract parameters for hardware implementation. In addition, the pictorial view of ASIC of the SS MODEM is also shown.