• 제목/요약/키워드: chip platform

검색결과 169건 처리시간 0.031초

정밀구동메커니즘 적용 모션제어시스템 설계 및 구현 (Design and Implementation for Motion Control System with Precise Driving Mechanism)

  • 이상경;이준영;최윤석;박홍배
    • 대한임베디드공학회논문지
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    • 제8권3호
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    • pp.129-136
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    • 2013
  • In this paper, a motion control system based on 2-axis gimbal system is designed and implemented to drive a high speed and precision. The proposed system consists of the RS-422 interface, 2-axis gimbal platform, servo control unit integrated with a high speed DSP chip-set, servo amplifier unit, potentiometer sensor unit, and resolver sensor unit. The servo control unit using the high speed DSP firmware is designed to get a fast response without an overshoot with step input and a RMS error of low probability with ramp input. The servo amplifier unit using a voltage control is designed to resolve the zero-crossing distortion for precise motion. To verify the performance and stability of the implemented system, experiments are performed through a measurement of the time and frequency domain response in a laboratory environment by using a PXI(PCI eXtentions for Instrumentation).

Comparison of Artificial Neural Networks for Low-Power ECG-Classification System

  • Rana, Amrita;Kim, Kyung Ki
    • 센서학회지
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    • 제29권1호
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    • pp.19-26
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    • 2020
  • Electrocardiogram (ECG) classification has become an essential task of modern day wearable devices, and can be used to detect cardiovascular diseases. State-of-the-art Artificial Intelligence (AI)-based ECG classifiers have been designed using various artificial neural networks (ANNs). Despite their high accuracy, ANNs require significant computational resources and power. Herein, three different ANNs have been compared: multilayer perceptron (MLP), convolutional neural network (CNN), and spiking neural network (SNN) only for the ECG classification. The ANN model has been developed in Python and Theano, trained on a central processing unit (CPU) platform, and deployed on a PYNQ-Z2 FPGA board to validate the model using a Jupyter notebook. Meanwhile, the hardware accelerator is designed with Overlay, which is a hardware library on PYNQ. For classification, the MIT-BIH dataset obtained from the Physionet library is used. The resulting ANN system can accurately classify four ECG types: normal, atrial premature contraction, left bundle branch block, and premature ventricular contraction. The performance of the ECG classifier models is evaluated based on accuracy and power. Among the three AI algorithms, the SNN requires the lowest power consumption of 0.226 W on-chip, followed by MLP (1.677 W), and CNN (2.266 W). However, the highest accuracy is achieved by the CNN (95%), followed by MLP (76%) and SNN (90%).

Software Design of CQUEAN

  • 정현주;박원기;김은빈;최창수;박수종;임명신;김정훈
    • 천문학회보
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    • 제35권1호
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    • pp.39.1-39.1
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    • 2010
  • We are developing a CCD camera named CQUEAN (Camera for Quasars in Early Universe) to search for quasars at z > 7. CQUEAN has a 1024*1024 deep depletion CCD chip and will be attached to 2.1m Otto-Struve Telescope at McDonald Observatory, USA. Although commercial software for the CCD camera is provided by the vendor, we are going to develop our own software to control the other instruments as well, to carry out efficient observation. There are four major parts in our software: Instrument control part controls the camera and filter wheel to obtain imaging data. Quick look window is to display acquired imaging data for quick inspection. Telescope control part interfaces with Telescope Control System (TCS) to move the telescope and to get time or coordinate information. Finally, Observation scripting facility part carries out a series of short exposures in a batch. The whole software will be written in python on linux platform, using the instrument control software libraries provided by the vendors.

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치과용 통합공급장치를 위한 안드로이드 운영체제가 내장된 제어시스템 개발 (Development of Control System with Android Operation System for Dentistry Integrated Device)

  • 황기현
    • 한국정보통신학회논문지
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    • 제16권3호
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    • pp.635-642
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    • 2012
  • 본 논문에서는 치과용 통합공급장치를 실시간으로 제어 및 모니터링할 수 있고 그 결과를 Wi-Fi 무선랜 통신을 통해 송수신이 가능한 제어시스템을 개발하였다. 개발한 제어시스템은 안드로이드 운영체제를 내장하기 위해 S3C6410 ARM 칩을 이용하여 설계하였다. 개발한 제어시스템은 Wi-Fi 통신, RS485, 리녹스 2.6 및 안드로이드 운영체제 2.0을 내장하도록 보드를 개발하였다. 개발한 제어시스템은 치과용 통합공급장치에 내장되어 있는 정수기, 컴프레서, 석션을 실시간으로 제어하였다. 실험결과, 개발한 제어시스템은 각 제어기 모듈과 연계하여 정수기, 석션 및 컴프레서를 실시간으로 제어하였고, 그 상태 값을 RS485 통신을 이용하여 제어시스템에 실시간으로 표시하였다.

Software Pipeline-Based Partitioning Method with Trade-Off between Workload Balance and Communication Optimization

  • Huang, Kai;Xiu, Siwen;Yu, Min;Zhang, Xiaomeng;Yan, Rongjie;Yan, Xiaolang;Liu, Zhili
    • ETRI Journal
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    • 제37권3호
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    • pp.562-572
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    • 2015
  • For a multiprocessor System-on-Chip (MPSoC) to achieve high performance via parallelism, we must consider how to partition a given application into different components and map the components onto multiple processors. In this paper, we propose a software pipeline-based partitioning method with cyclic dependent task management and communication optimization. During task partitioning, simultaneously considering computation load balance and communication optimization can cause interference, which leads to performance loss. To address this issue, we formulate their constraints and apply an integer linear programming approach to find an optimal partitioning result - one that requires a trade-off between these two factors. Experimental results on a reconfigurable MPSoC platform demonstrate the effectiveness of the proposed method, with 20% to 40% performance improvements compared to a traditional software pipeline-based partitioning method.

지능형 디지탈홈을 위한 콤퍼짓 센서제어네트워크 및 테스트베드의 연구 (A Study of a Composite Sensor and Control Network and Its Test-bed for the Intelligent and Digital Home)

  • 이규호
    • 한국정보통신학회논문지
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    • 제11권9호
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    • pp.1687-1693
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    • 2007
  • 네트워크 기술이나 반도체 집적기술, 그리고 임베디드 시스템 기술의 발달로 넓은 범위의 영역에서 센서네트워크 활용이 가능해졌다. 따라서 센서 네트워크는 그것이 적용되는 응용분야에 따라서 여러 가지 형태와 차별화 된 특성으로 다양화되고 있다. 지능형 디지털 홈은 고유한 특성의 센서네트워크를 구성할 수 있는 한 분야이다. 본 논문에서는 컴퍼짓 센서 및 제어 네트워크를 제안하고, 이의 차세대 지능형 홈 네트워크 적용에 대해 논의한다. 또한 제안된 네트워크의 개발결과와 이를 기반으로 한 지능형 홈 서비스, 그리고 가상시험환경인 테스트베드의 개발결과를 제시한다.

Development of a low-cost multifunctional wireless impedance sensor node

  • Min, Jiyoung;Park, Seunghee;Yun, Chung-Bang;Song, Byunghun
    • Smart Structures and Systems
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    • 제6권5_6호
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    • pp.689-709
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    • 2010
  • In this paper, a low cost, low power but multifunctional wireless sensor node is presented for the impedance-based SHM using piezoelectric sensors. Firstly, a miniaturized impedance measuring chip device is utilized for low cost and low power structural excitation/sensing. Then, structural damage detection/sensor self-diagnosis algorithms are embedded on the on-board microcontroller. This sensor node uses the power harvested from the solar energy to measure and analyze the impedance data. Simultaneously it monitors temperature on the structure near the piezoelectric sensor and battery power consumption. The wireless sensor node is based on the TinyOS platform for operation, and users can take MATLAB$^{(R)}$ interface for the control of the sensor node through serial communication. In order to validate the performance of this multifunctional wireless impedance sensor node, a series of experimental studies have been carried out for detecting loose bolts and crack damages on lab-scale steel structural members as well as on real steel bridge and building structures. It has been found that the proposed sensor nodes can be effectively used for local wireless health monitoring of structural components and for constructing a low-cost and multifunctional SHM system as "place and forget" wireless sensors.

스마트기기용 강압형 DC-DC 변환기 특성해석 (Analysis of a Buck DC-DC Converter for Smart Electronic Applications)

  • 강보경;나재훈;송한정
    • 한국산업융합학회 논문집
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    • 제22권3호
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    • pp.373-379
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    • 2019
  • Nowadays, the IoT portable electronic devices have become more useful and diverse, so they require various supply voltage levels to operate. This paper presents a DC-DC buck converter with pulse width modulation (PWM) for portable electronic devices. The proposed step-down DC-DC converter consists of passive elements such as capacitors, inductors, and resistors and an integrated chip (IC) for signal control to reduce power consumption and improves ripple voltage with the resolution. The proposed DC-DC converter is simulated and analyzed in PSPICE circuit design platform, and implemented on the prototype PCB board with a Texas Instruments LM5165 IC. The proposed buck converter is showed 92.6% of peak efficiency including a load current range of 4-10 mA, 3.29 mV of the voltage ripple at 5 V output voltage for the supply voltage 12 V. Measured and Simulated power efficiency are made good agreement with each other.

Comparison of the Performance of MiSeq and HiSeq 2500 in a Microbiome Study

  • Na, Hee Sam;Yu, Yeuni;Kim, Si Yeong;Lee, Jae-Hyung;Chung, Jin
    • 한국미생물·생명공학회지
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    • 제48권4호
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    • pp.574-581
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    • 2020
  • Next generation sequencing is commonly used to characterize the microbiome structure. MiSeq is commonly used to analyze the microbiome due to its relatively long read length. However, recently, Illumina introduced the 250x2 chip for HiSeq 2500. The purpose of this study was to compare the performance of MiSeq and HiSeq in the context of oral microbiome samples. The MiSeq Reagent Kit V3 and the HiSeq Rapid SBS Kit V2 were used for MiSeq and HiSeq 2500 analyses, respectively. Total read count, read quality score, relative bacterial abundance, community diversity, and relative abundance correlation were analyzed. HiSeq produced significantly more read sequences and assigned taxa compared to MiSeq. Conversely, community diversity was similar in the context of MiSeq and HiSeq. However, depending on the relative abundance, the correlation between the two platforms differed. The correlation between HiSeq and MiSeq sequencing data for highly abundant taxa (> 2%), low abundant taxa (2-0.2%), and rare taxa (0.2% >) was 0.994, 0.860, and 0.416, respectively. Therefore, HiSeq 2500 may also be compatible for microbiome studies. Importantly, the HiSeq platform may allow a high-resolution massive parallel sequencing for the detection of rare taxa.

블라인드 워터마킹을 내장한 실시간 비디오 코덱의 FPGA기반 단일 칩 구조 및 설계 (FPGA-based One-Chip Architecture and Design of Real-time Video CODEC with Embedded Blind Watermarking)

  • 서영호;김대경;유지상;김동욱
    • 한국통신학회논문지
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    • 제29권8C호
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    • pp.1113-1124
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    • 2004
  • 본 논문에서는 입력 영상을 실시간으로 압축 및 복원할 수 있는 하드웨어(hardware, H/W)의 구조를 제안하고 처리되는 영상의 보안 및 보호를 위한 워터마킹 기법(watermarking)을 제안하여 H/W로 내장하고자 한다. 영상압축과 복원과정을 하나의 FPGA 칩 내에서 처리할 수 있도록 요구되는 모든 영상처리 요소를 고려하였고 VHDL(VHSIC Hardware Description Language)을 사용하여 각각을 효율적인 구조의 H/W로 사상하였다. 필터링과 양자화 과정을 거친 다음에 워터마킹을 수행하여 최소의 화질 감소를 가지고 양자화 과정에 의해 워터마크의 소실이 없으면서 실시간으로 동작이 가능하도록 하였다. 구현된 하드웨어는 크게 데이터 패스부(data path part)와 제어부(Main Controller, Memory Controller)로 구분되고 데이터 패스부는 영상처리 블록과 데이터처리 블록으로 나누어진다. H/W 구현을 위해 알고리즘의 기능적인 간략화를 고려하여 H/W의 구조에 반영하였다. 동작은 크게 영상의 압축과 복원과정으로 구분되고 영상의 압축 시 대기지연 시간 없이 워터마킹이 수행되며 전체 동작은 A/D 변환기에 동기하여 필드단위의 동작을 수행한다. 구현된 H/W는 APEX20KC EP20K600CB652-7 FPGA 칩에서 69%(16980개)의 LAB(Logic Array Block)와 9%(28352개)의 ESB(Embedded System Block)을 사용하였고 최대 약 82MHz의 클록주파수에서 안정적으로 동작할 수 있어 초당 67필드(33 프레임)의 영상에 대해 워터마킹과 압축을 실시간으로 수행할 수 있었다.