• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• Genomics & Informatics
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• v.5 no.2
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• pp.83-87
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• 2007

The analysis of DNA microarray data is a rapidly evolving area of bioinformatics, and various types of microarray are emerging as some of the most exciting technologies for use in biological and clinical research. In recent years, microarray technology has been utilized in various applications such as the profiling of mRNAs, assessment of DNA copy number, genotyping, and detection of methylated sequences. However, the analysis of these heterogeneous microarray platform experiments does not need to be performed separately. Rather, these platforms can be co-analyzed in combination, for cross-validation. There are a number of separate laboratory information management systems (LIMS) that individually address some of the needs for each platform. However, to our knowledge there are no unified LIMS systems capable of organizing all of the information regarding multi-platform microarray experiments, while additionally integrating this information with tools to perform the analysis. In order to address these requirements, we developed a web-based LIMS system that provides an integrated framework for storing and analyzing microarray information generated by the various platforms. This system enables an easy integration of modules that transform, analyze and/or visualize multi-platform microarray data.

• Journal of the Korean Society of Visualization
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• v.18 no.3
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• pp.84-89
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• 2020

Cancer cells secrete angiogenic factors, and nearby vasculatures make new blood vessels essential for cancer development and metastasis in response to these soluble factors. Many efforts have been made to elucidate cancer-endothelial cell interactions in vitro. However, not much is known due to the lack of a suitable co-culture platform. Here, we introduce a 3D printing-based microfluidic system that mimics the in vivo-like cancer-endothelial cell interactions. The tumoroids and endothelial cells are co-cultured, physically separated by porous fibrin gel, allowing communication between two cell types through soluble factors. Using this microfluidic system, we were able to visualize new vessel formation induced by tumoroids of different origins, including liver, breast, and ovary. We confirmed that the ovarian tumoroids most induced angiogenesis while the other two cancer types suppressed it. Utilization of the proposed co-culture platform will help the researchers unveil the underlying mechanisms of the dynamic interplay between tumor and angiogenesis.

• ETRI Journal
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• v.27 no.3
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• pp.337-340
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• 2005

A spot-size converted Fabry-Perot laser diode (LD) was flip-chip bonded to a silica-terraced planar lightwave circuit(PLC) platform to examine the effect of the silica terrace on the heat dissipation of the LD module. From the measurement of the light-current characteristics, it was discovered that the silica terrace itself is not a strong thermal barrier, but the encapsulation of the integrated LD with an index-matching polymer resin more or less deteriorates the heat dissipation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.127-138
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• 2012

In this paper, we propose a real-time virtual re-convergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our unique idea to reduce visual fatigue is to utilize the virtual re-convergence based on the optimized disparity-map that contains more depth information in the negative disparity area than in the positive area. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth post-processing, and virtual view control, is realized in real time with 60 fps on a single Xilinx Virtex-5 FPGA chip.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.11
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• pp.1018-1026
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• 2012

This paper presents a developing method of smart fingerprint recognition system. First, we design a hardware configuration circuit using a 32bit Risc CPU, a fingerprint sensor, a LCD, and a WiFi communication chip to realize the smart fingerprint recognition systems. It is necessary to develop a JNI (Java Native Interface) library and a device drive program of fingerprint sense to develop application program of fingerprint recognition system with Android platform. Thus second, we develop a device drive and a JNI program. And we also develop an application program of fingerprint recognition systems using developed JNI library. Finally test results are presented to illustrate the performance of the developed smart fingerprint recognition system.

• The Magazine of the IEIE
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• v.30 no.9
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• pp.28-28
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• 2003

SoC(System on Chip)의 발전은 현재 널리 쓰이는 기존의 설계 방법론으로는 해결될 수 없는 여러 가지 문제들을 생성하고 있다. 제품의 복잡도는 급격히 증가하는 반면 제품 수명은 지속적으로 감소하고 있으며, 기존 구현 기술의 향상만으로는 해결하기 쉽지 않은 VDSM (Very Deep Sub-Micron) 문제 또한 새로이 도출되고 있는 실정이다. 이러한 문제들은 적기에 시장에 제품을 출시하는 데에 많은 어려움을 끼치게 되기 때문에, 기존의 방법론을 뛰어 넘는 새로운 설계 방법론을 위한 많은 연구들이 활발히 진행되고 있다. 이러한 방법론 중 효율적인 한 방안으로 "재사용"의 개념이 대두되고 있으며, platform-based design은 이러한 재사용의 개념을 SoC 설계에 효율적으로 적용할 수 있는 방법으로 많은 관심을 받고 있다. 본 논문은 이러한 platform-based design의 최근 동향 및 현재 삼성전자에서 추진하고 있는 platform-based design에 대해 기술한다.

• The Magazine of the IEIE
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• v.30 no.9
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• pp.934-941
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• 2003

SoC(System on Chip)의 발전은 현재 널리 쓰이는 기존의 설계 방법론으로는 해결될 수 없는 여러 가지 문제들을 생성하고 있다. 제품의 복잡도는 급격히 증가하는 반면 제품 수명은 지속적으로 감소하고 있으며, 기존 구현 기술의 향상만으로는 해결하기 쉽지 않은 VDSM (Very Deep Sub-Micron) 문제 또한 새로이 도출되고 있는 실정이다. 이러한 문제들은 적기에 시장에 제품을 출시하는 데에 많은 어려움을 끼치게 되기 때문에, 기존의 방법론을 뛰어 넘는 새로운 설계 방법론을 위한 많은 연구들이 활발히 진행되고 있다. 이러한 방법론 중 효율적인 한 방안으로 "재사용"의 개념이 대두되고 있으며, platform-based design은 이러한 재사용의 개념을 SoC 설계에 효율적으로 적용할 수 있는 방법으로 많은 관심을 받고 있다. 본 논문은 이러한 platform-based design의 최근 동향 및 현재 삼성전자에서 추진하고 있는 platform-based design에 대해 기술한다.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.500-502
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• 2003

In this paper, we have designed a platform with MSC8101 processor for networked converter monitoring and diagnosis. MSC8101 is a dual processor type SOC(System On a Chip), which is consist of 16bit DSP and 32bit RISK CPM. As it have DSP and CPM, MSC8101 is competent for networking and data processing application. This MSC8101 platform is designed for networked monitoring and diagnosis, so it is important processing ability and networking capability.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.696-706
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• 2007

Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.