• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1378-1385
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• 1990

In this paper we propose a model which can predict well the logical errors come from the charge redistribution in domino gates. In this model the effect of the intrinsic capacitance between gate and channel of MOSFET's is considered. This effect is more important than the parasitic capacitance effect. The error by the proposed model is only 8% of that by the currently used model. This model can be used as a guide-line in the design of domino circuits.

• Proceedings of the Korean Vacuum Society Conference
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• 2003.02a
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• pp.35-35
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• 2003

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.65-71
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• 2005

Physical signals generated in the real world are transformed into electrical signals through sensors and fed into electronic circuits. The electrical signals input to electronic circuits are in analog form, thus they must be converted to digital signals using an ADC(Analog-Digital Converter) for digital processing. Signal processing circuits and ADCs that are to be integrated on a single chip together with silicon micro sensors should be designed to have less silicon area and less power consumption. This paper proposed a charge redistribution ADC which reduces silicon area considerably. The proposed method achieves 8 bit conversion by performing 4-bit conversion twice. It reduced the area of capacitor array, which takes most of the ADC area, by 1/16 when compared to a conventional method. Though it uses twice the number of clocks as a conventional method, it would be appropriate to be integrated with a silicon pressure sensor on a single chip since it does not demand high conversion rate.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.171-171
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• 1999

We studied the charge redistribution in the Pt-M (M=Cu, Co) alloys by X-ray Absorption Near Edge Spectroscopy(XANES) and X-ray Photoelectron Spectroscopy(XPS). These analysis tools provide us information about the charge transfer in the valence band of intermetallic bonding. The samples were prepared by arc-melting method. After annealing this samples in vacuum for several hours, we cold get the ordered samples, which were confirmed with XRD analysis. the core and valence level energy shift in these system were investigated by Mg $K\alpha$(1253.6eV) x-ray source for Pt-Co alloys and monochromatized Al $K\alpha$ (1486.6eV) for Pt-Cu alloys. Pt L2, L3-edge, and Cu, Co K-edge XANES spectra were measured with the total electron-yield mode detector at the 3Cl beam line of the PLS (Pohang light source0. from the changes of White line (WL) area and the core level shifts of the each metal sites, we can obtain the information about the electrons participating in the intermetallic bonding of the Pt-Cu and Pt-Co alloys.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• Journal of Science Education
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• v.46 no.2
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• pp.212-221
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• 2022

In this study, we propose an analytical model to elucidate the formation of electric fields between two parallel conducting plates. Using nine Gaussian surfaces, we investigated the charge redistributions and electric fields formed by parallel conducting plates when two charged plates get close together. The electric charges are redistributed via a new electrostatic equilibrium to create the electric field of each plates. As a result, the electric field start from + electrode plate to - electrode plate via inducing a new electrostatic equilibrium, implying that the application of Gaussian surfaces to only one of the electrodes of parallel-plate capacitors is deserved. The results will help undergraduate students understand the charge redistribution and the electric field formation in parallel-plate capacitors in a reasonable manner.

• The Korean Journal of Applied Statistics
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• v.28 no.4
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• pp.721-739
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• 2015

The importance of the old age income security will increase for an aging society due to the deepening income polarization. The National Pension(NP) is a representative Social Security scheme in charge of old age income security as well as income redistribution for the insured. Studies by Kim (2002), Kim et al. (2003), and Hong (2013) have reported the possibility of unsatisfactory income redistribution of the NP. Recently Choi (2015) attributed those results to an unnoticed defect in the benefit formula. This study is a test for the unsatisfactory income redistribution of the current National Pension using early participants who have now become pensioners. The method aggregates cohorts and combines individual history data before the year 2013 and the results of the actuarial projection model of the 2013 after the year 2014. The results are divided by measures taken. The redistribution is obviously progressive by the income replacement rate; however, it is significantly regressive when measured by the net benefit theoretically as more plausible. Considering the effect of differing lifetime contribution year among income classes, the regressive redistribution will prevail more in the future pensioners.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1311-1313
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• 1997

We describe the working principle, the design, and the characteristics of two-chip integrated humidity sensor. The sensing element was manufactured using polyimide. The interface circuits were developed based on a charge redistribution between capacitors. The sensor and signal conditioning chips were packaged together in the same package. The sensor showed excellent linearity over a wide range of relative humidity.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1388-1390
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• 1994

A polyimide-based capacitive humidity sensor has been designed and fabricated using silicon integrated-circuit technology, and its performance measured. The sensor showed excellent linearity, low temperature coefficient, and low hysteresis over a wide range of relative humidity and temperature. The signal conditioning circuits for detecting relative humidity and converting it to voltage have been developed based on a charge redistribution between capacitors using switched -capacitors.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1606-1616
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• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.