• Proceedings of the KIEE Conference
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• 2008.10a
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• pp.161-162
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• 2008

본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed RFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블록은 Cadence spectre를 이용하여 검증하였다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.8
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• pp.1-7
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• 2012

In this paper, a new LED driving circuit which is able to control dimming of LED is proposed using charge pump. The proposed LED driving circuit steps down the input voltage to operate LED without DC-DC converter. The operation of this driving circuit is verified by P-Spice simulation, and the characteristics of the driving circuit is measured and evaluated in the experiments. As a result, the driving circuit efficiency of 88.5[%] is obtained when all LEDs are turned on by digital control method at the highest dimming level(255/255).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1353-1359
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• 2001

본 논문에서는 위상획득과정과 동기과정에서 trade-off 현상을 향상시킨 듀얼 위상 주파수 검출기를 제안하여 차지펌프 PLL을 설계하였다. 듀얼 위상 주파수 검출기는 상승에지에서 동작하는 POSITIVE 위상 주파수 검출기와 하강에지에서 동작하는 NEGATIVE 위상 주파수 검출기로 구성되어 있다. 제안한 차지펌프는 전류뺄셈회로를 이용하여 전류 부정합을 감소시켰으며, reference spurs와 전압제어발진기의 변동을 감소시킬 수 있도록 구현하였다. 제안한 차지펌프 PLL은 0.25$\mu\textrm{m}$ CMOS 공정을 사용하여 SPICE로 시뮬레이션 하였으며, 그 결과 1.6~1.85GHz의 넓은 동기범위를 나타내었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1267-1270
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• 2006

Organic light-emitting diode (OLED) display panel with $64\;{\times}\;64$ pixels utilizing the charge-pump (CP) pixel addressing method was fabricated using conventional thin-film processes. Each pixel consists of a-Si:H Schottky diode and $ITO/SiO_2/ITO$ capacitor. It is shown that CP-OLED is technically feasible for information display and a driving voltage below $4V_{pp}$ is enough for nominal operation.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2798-2800
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• 1999

A new circuit, modified valley fill (MVF) combined with resonant inductor of the self-excited resonant inverter and charge pump capacitors(CPCs), is presented to achieve high PF electronic ballast providing sufficient preheat current to lamp filaments for soft start maintaining low DC bus voltage. The MVF can adjust the valley voltage higher than half the peak line voltage. The CPCs draw the current from the input line to make up the current waveform during the valley interval. The measured PF and THD are 0.99 and 12%, respectively. The lamp current CF is also acceptable in the proposed circuit. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.340-343
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• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.664-670
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• 2015

A four-times-VDD switch that supports high and low voltage mode operations is demonstrated in a generic 65 nm logic process. The proposed switch shows the robust operation for supply voltages ranging from VDD to $4{\times}VDD$. A cascaded voltage switch and a voltage doubler based charge pump generate the intermediate supply voltage levels required for the proposed high voltage switch. All the high voltage circuits developed in this work can be implemented using standard logic transistors without being subject to any voltage overstress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.41-42
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• 2009

This paper presents a motor drive IC for automotive applications. The drive IC is dedicated to control and drive external MOSFETs which directly drive 3-phase motor with a high current. In case of driving high-side power switches, the bootstrap topology is widely used. However, it requires three bootstrap diode and three capacitor respectively. And it needs a minimum charging time to maintain high-side voltage. The motor drive IC uses a charge-pump circuit for all three high-side voltage with various protection schemes for automotive applications.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1386-1388
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• 2008

본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed PFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블락은 Cadence spectre 를 이용하여 검증하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.108-112
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• 2002

A new pixel driving method for organic light-emitting diode (OLED) flat-panel display (FPD) is proposed. The new charge-pump passive-matrix pixel driver consists only of a storage capacitance and a rectifying diode, and no thin-film transistor (TFT) is needed. The new driver not only supplies a constant current to the OLED throughout the whole period of panel scanning like an active-matrix driver, but also provides a highly linear gray-scale control through a pure digital manner.