• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.85-92
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• 2009

This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.45-53
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• 2015

Adaptive support-weight based algorithm can produce better disparity map compared to generic area-based algorithms and also can be implemented as a realtime system. In this paper, we propose a realtime system based on geodesic support-weight which performs better segmentation of objects in the window. The data scheduling is analyzed for efficient hardware design and better performance and the parallel architecture for weight update which takes the longest delay is proposed. The exponential function is efficiently designed using a simple step function by careful error analysis. The proposed architecture is designed with verilogHDL and synthesized using Donbu Hitek 0.18um standard cell library. The proposed system shows 2.22% of error rate and can run up to 260Mhz (25fps) operation frequency with 182K gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.12
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• pp.1138-1147
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• 2012

IEEE standard 802.16, often referred to as WiMAX, is considered a "last mile" broadband wireless access alternative to conventional DSL and Cable Internet. One extension that is recently receiving great attention is the IEEE 802.16j Mobile Multihop Relay (MMR) amendment. The focus of this amendment is the development of simple and lower cost relay stations (RSs) that can enhance network coverage and capacity. We use our proposed simple scheduling scheme for serving the SSs in a fair manner and evaluate the performance of WiMAX networks with relays, especially we analyze the impact of interference between RSs on cell throughput Through simulations and numerical analysis, we make several fundamental observations about interference aware cost effective coverage extension in such networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1844-1850
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• 2016

The bilateral filter can reduce the noise while preserving details computing the filtering output at each pixels as the average of neighboring pixels. In this paper, we propose a real-time system based on window division. Overall performance is increased due to the parallel architectures which computes five rows in the kernel window simultaneously but with pipelined scheduling. We consider the tradeoff between the filter performance and the hardware cost and the bit allocation has been determined by PSNR analysis. The proposed architecture is designed with verilogHDL and synthesized using Dongbu Hitek 110nm standard cell library. The proposed architecture shows 416Mpixels/s (397fps) of throughput at 416MHz of operating frequency with 132K gates.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.103-103
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• 2000

In this paper to cope with the reduction of products life-cycle as the variety of products along with the various demands of consumers, a virtual simulator is developed to make the changeover of manufacturing line efficient to embody a virtual simulation similar to a real manufacturing line. The developed virtual simulator can design a layout of a factory and make the time scheduling. Every factory has one simulator so that one product can be manufactured in the factories to use them as virtual factories. We suggest a scheme that heightens the agility to the diversity of manufacturing models by making the information of manufacturing lines and products models to be shared. The developed unit simulator can construct a proper virtual manufacturing line along with the required process of products using several kinds of operator and work cell. A user with the simulator can utilize an interface that makes one to manage the separate task process for each manu(acturing module, change operator components and work cells, and easily teach tasks of each task module. The developed simulator was made for users convenience by Microsoft Visual C++ 6.0 that can develop a program supplying graphic user interface environment and by OpenGL of the Silicon Graphics as a graphic library to embody 3D graphic environment. Also, we show that the simulator can be used efficiently for the agile manufacturing by the communication among the factories being linked by TCP/IP and a hybrid database system made by a hierarchical model and a relational model being developed to standardize the data information.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1514-1525
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• 1998

Two main characteristics of VBR MPEG video traffic are different statistics according to different picture types and the periodic traffic pattern due to GOP structure. Especially, the I-pictures at the beginning of each GOP generate $$\mu$h more traffic than other pictures. When several VBR Mpeg video sources are superposed, the I-picture starting times of these sources may significantly affect the cell loss characteristics of ATM $$\mu$tiplexers. In this paper, we propse a performance model for ATM $$\mu$tiplexers with VBR MPEG video sources whose starting times are arbitrary given. For analysis, both single and superposed source traffic are modeled as NDPPs (non-deterministic periodic processes), and the ATM $$\mu$tiplexer is modeled as a U-state NDPPD/D/1/B queueing system. It is hown that the numerical results are very close to the si$$\mu$ation results. From the relationships between the starting tiem distributions and the corresponding $$\mu$tiplexer performances, some considerations for designing a scheduling policy in order to obtain the maxi$$\mu$ $$\mu$tiplexing gain are presented.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.90-98
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• 2013

The stereo system based on local matching is very popular due to its algorithmic simplicity, however it is limited to apply to various applications because it shows poor quality with low matching rates. In this paper, we propose and design a realtime stereo system based on an adaptive support-weight and the system shows low error rates and realtime performance. Generally, in the adaptive support-weight algorithm the intermediate computing results can not be reused to reduce the number of computations. In this research we modify the scheduling to reuse the intermediate results for the better performance by processing rows and columns separately. The nonlinear functions such as exponential or arc tangent have been designed with piecewise linear and step functions by empirical simulations and error analysis. The proposed architecture is composed of 9 processing elements for realtime performance. The proposed stereo system has been designed and synthesized using Donbu Hitek 0.18um standard cell library and can run up to 350Mhz operation frequency (33 frames per second) with 424K gates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of Positioning, Navigation, and Timing
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• v.7 no.2
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• pp.53-59
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• 2018

This paper proposes a pseudo-random beamforming technique for time-synchronized mobile base stations (BSs) for multi-cell downlink networks which have mobility. The base stations equipped with multi-antennas and mobile stations (MSs) are time-synchronized based on global positioning system (GPS) signals and generate a number of transmit beamforming matrix candidates according to the predetermined pseudo-random pattern. In addition, MSs generate receive beamforming vectors that correspond to the beam index number based on the minimum mean square error (MMSE) using transmit beamforming vectors that make up a number of transmit beamforming matrices and wireless channel matrices from BSs estimated via the reference signals (RS). Afterward, values of received signal-to-interference-plus-noise ratio (SINR) with regard to all transmit beamforming vectors are calculated, and the resulting values are then feedbacked to the BS of the same cells along with the beam index number. Each of the BSs calculates each of the sum-rates of the transmit beamforming matrix candidates based on the feedback information and then transmits the calculated results to the BS coordinator. After this, optimum transmit beamforming matrices, which can maximize a sum-rate of the entire cells, are selected at the BS coordinator and informed to the BSs. Finally, data signals are transmitted using them. The simulation results verified that a sum-rate of the entire cells was improved as the number of transmit beamforming matrix candidates increased. It was also found that if the received SINR values and beam index numbers are feedbacked opportunistically from each of the MSs to the BSs, not only nearly the same performance in sum-rate with that of applying existing feedback techniques could be achieved but also an amount of feedback was significantly reduced.

• Journal of the Korea Society of Computer and Information
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• v.15 no.6
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• pp.49-56
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• 2010

In this paper, a joint PHY-MAC layer optimized resource allocation scheme for OFDMA based micro base stations is investigated. We propose cross-layer optimized two-stage resource allocation scheme including cross-layer functional description and control information flow between PHY-MAC layers. The proposed two-stage resource allocation scheme consists of a user grouping stage and a resource allocation stage. In the user grouping stage, users are divided into a macro base station user group and a micro base station user group based on the PHY-MAC layer characteristics of each user. In the resource allocation stage, a scheduling scheme and an allotment of resources are determined. In the proposed scheme, diversity and adaptive modulation and coding (AMC) schemes are exploited as schedulers. Simulation results demonstrate that the proposed scheme increases the average cell throughput about 40~80 % compared to the conventional system without micro base stations.