• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

• 한국조경학회지
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• 제33권1호
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• pp.58-70
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• 2005

Management practices and ordinances for urban scenic view protection are varied by cities because they have their distinctive nature and social environment. Therefore landscape management methods for urban scenic views are generally varied by the characteristics of city landscape and ordinance. This case study for scenic view protection practices in U.S.A. is very meaningful and appropriate because cities initiate a plan and/or an ordinance to manage urban scenic view in Korea. Urban scenic view protection methods were analyzed based on followings: 1) how to select scenic view resources and define spatial areas for preserving them, 2) how to control building height, open view corridor and guide landscaping and 3) how to carry out view protection methods and organize them in laws or ordinances. Findings of this study will be applied usefully in the development of urban scenic view protection methods in Korea.

• 한국기계가공학회지
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• 제9권3호
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• pp.1-7
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• 2010

The aim of this research is to evaluate movement and path characteristics of developed heavy duty handling robot using laser tracker(API T3) according to the ISO 9283 robot performance evaluation criteria. As carry out 3D modeling and simulation using CATIA, a test cube was set up to select moving and measuring range of robot. Performance test for pose and distance accuracy, path and path velocity accuracy under payload zero and 440kgf was accomplished. The resulted output data show the reliability of the developed robot.

• 한국콘텐츠학회:학술대회논문집
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• 한국콘텐츠학회 2007년도 추계 종합학술대회 논문집
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• pp.265-269
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• 2007

현재 e-Science에 대한 관심이 높아지면서, e-Science 사업의 성공적 추진을 위한 사업기획이 중요해지고 있다. 현재 대규모 투자가 필요한 e-Science의 성격상, e-Science 성숙단계, 추진방법, 과제의 특성 등에 따른 적절한 응용과제의 선정이 필요하다. 응용과제의 선정을 통해 연구과제를 IT기반으로 적용, 수행 할 수 있는 e-Science 관련요소기술의 개발, 인프라 연동계획 등 연구실시계획이 수립 될 수 있다. 본 연구에서는 e-Science 응용연구 과제 선정을 위한 후보 과제 풀을 국가연구개발사업 및 기술예측과제 등 유망 기술과제에서 도출, 과제의 선정평가를 위한 모형과 추진 방안을 논의해 본다.

• 전자공학회논문지A
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• 제28A권11호
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• pp.915-922
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• 1991

This research paper presents an ALU unit using 1.0$\mu$m CMOS technology capable of doing IEEE standard single and double precision floating poing calculation within 32ns (2 clock) at 60 MHz clock speed. This 32ns speed was achieved by using 9ns 1's complement arithmetic 54 bit carry select adder instead of previous 2's complement adders. On the first cycle, this adder is used for addition or subtraction and the second cycle uses this adder for rounding. This reduces the number of required adders from two to one. Speed improvement is 2 to 5 times compared with previous 40MHz design. Design goal was 60MHz, however, this unit is functioning at 80 MHz at room temperature.

• 전자공학회논문지C
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• 제34C권11호
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• pp.47-55
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• 1997

In general, processing flow of the conventional floating-point multiplication consists of either multiplication, addition, normalization, and rounding stage of the conventional floating-point multiplier requries a high speed adder for increment, increasing the overall execution time and occuping a large amount of chip area. A floating-point multiplier performing addition and IEEE rounding in parallel is designed by using the carry select addder used in the addition stage and optimizing the operational flow based on the charcteristics of floating point multiplication operation. A hardware model for the floating point multiplier is proposed and its operational model is algebraically analyzed in this paper. The proposed floating point multiplier does not require and additional execution time nor any high spped adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this suggested approach.

• 전자공학회논문지B
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• 제32B권3호
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• pp.24-30
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• 1995

The process of conventional floating-point additio $n_traction operation consists of alignment, additio $n_traction, normalization, and rounding stage. Because rounding stage needs an incrementor or adder, it occupies much time and chip area. In addition, it needs additional time and hardware for renormalization which occurs in overflow due to rounding In this paper, floating-point adde $r_tractor performing rounding and additio $n_traction in parallel is presented by using the feature of additio $n_traction and carry select adder used in additio $n_tracting stage. Proposed floating point adde $r_tractor doesn't need time and incrementor nor adder for rounding. Also, renormalization doesn't occur since rounding is performed prior to normalization.to normalization.

• 한국지능정보시스템학회:학술대회논문집
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• 한국지능정보시스템학회 2006년도 춘계학술대회
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• pp.311-315
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• 2006

Viterbi decoder는 크게 BM(Branch metric), ACS(Add-Compare-Select), SM(Survivor Memory) block 으로 구성되어 있다. 이중 ACSU 부분은 고속 데이터 처리를 위한 bottleneck이 되어 왔으며, 이의 해결을 위한 많은 연구가 활발히 진행되어 왔다. look ahead technique은 ACSU를 M-step으로 처리하고 CS(Carry save) number를 사용한 새로운 비교 알고리즘을 제안하여 high throughput을 추구했으며, minimized method는 block processing 방식으로 forward, backward 방향으로 decoding을 수행하여 ACSU 부분의 feedback을 완전히 제거하여 exteremely high throughput 을 추구하고 있다. 이에 대해 look ahead technique 의 기본 PE(Processing Element)를 바탕으로 minimized method 알고 리즘의 core block 을 bit-level 로 구현하였으며 : code converter 를 이용하여 CS number 가운데 redundat number(l)를 제거하여 비교기를 더 간단히 하였다. SYNOPSYS의 Design compiler 와 TSMC 0.18 um library 를 이용하여 합성하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 D
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• pp.948-950
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• 1997

This paper presents a basic interposing logic program to control nuclear power plant. In this paper we select a target control loop among the whole interposing modules, develop logic algorithm and functional software to compose target control loop. After that we carry out V&V(Verification and Validation) into the developed logic program to improve quality and reliability.

• 대한치과보존학회:학술대회논문집
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• 대한치과보존학회 2001년도 춘계학술대회
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• pp.258-258
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• 2001

Fiber-reinforced materials have highly favorable mechanical properties. and their strength-to-weight ratios are superior to those of most alloys. When compared to metals they offer many other advantages as well. including non-corrosiveness. translucency. good bonding properties. and ease ofrepair. Fiber-reinforced materials can be categorized to pre-impregnated. impregnation required. dental laboratory products. chairside products and prefabricated posts. so it is not suprising that fiber-reinforced composites have potential for use in many applications in dentistry. Fiber-reinforced materials can be utilized in frameworks for crowns. anterior or posterior fixed prostheses. chairs ide tooth replacements. periodontal splints. customized posts. prefabricated posts. orthodontic retention. denture reinforcements and in implants dentistry. To realize the full potential of using fiber-reinforced composite restorations. it is essential that the clinician and laboratory technician understand concepts of tooth preparation and framework design. Also practitioner may appreciate the background information and other details about the materials themselves so that identify the rationale for their use in various clinical situations. select well-suited materials. and carry out related procedures. Understanding the material properties and take many attentions. fiber-reinforced materials will give more esthetic. more easy. more strong and more reliable restorations.ations.