• Title/Summary/Keyword: carbon nanotube array

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Enhanced Electron Emission of Carbon Nanotube Arrays Grown Using the Resist-Protection-assisted Positioning Technique

  • Ryu, Je-Hwang;Kim, Ki-Seo;Yu, Yi-Yin;Lee, Chang-Seok;Lee, Yi-Sang;Jang, Jin;Park, Kyu-Chang
    • Journal of Information Display
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    • v.9 no.4
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    • pp.30-34
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    • 2008
  • Field emitter arrays (FEAs) were developed using carbon nanotubes (CNTs) as electron emission sources. The CNTs were grown using a selective-positioning technique with a resist-protection layer. The light emission properties were studied through the electron emission of the CNTs on patterned islands, which were modulated with island diameter and spacing. The electron emission of CNT arrays with $5{\mu}m$ diameters and $10{\mu}m$ heights increased with increased spacing (from $10{\mu}m$ to $40{\mu}m$). The electron emission current of the $40-{\mu}m$-island-spacing sample showed a current density of 1.33 mA/$cm^2$ at E = 11 V/${\mu}m$, and a turn-on field of 7 V/${\mu}m$ at $1{\mu}A$ emission current. Uniform electron emission current and light emission were achieved with $40{\mu}m$ island spacing and $5{\mu}m$ island diameter.

Novel Design of 8T Ternary SRAM for Low Power Sensor System

  • Jihyeong Yun;Sunmean Kim
    • Journal of Sensor Science and Technology
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    • v.33 no.3
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    • pp.152-157
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    • 2024
  • In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTI and NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic '0' or '2,' the proposed SRAM cell operates the same way as conventional binary SRAM. For logic '1,' it works differently as storage nodes on each side retain voltages of VDD/2 and VDD, respectively, using the subthreshold current of two additional transistors. By applying the ternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and the proposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in static power consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of the cell operation when VDD is set to 0.9 V.

Fabrication of Field Emitter Arrays by Transferring Filtered Carbon Nanotubes onto Conducting Substrates

  • Jang, Eun-Soo;Goak, Jung-Choon;Lee, Han-Sung;Lee, Seung-Ho;Lee, Nae-Sung
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.311-311
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    • 2009
  • Carbon nanotubes (CNTs) belong to an ideal material for field emitters because of their superior electrical, mechanical, and chemical properties together with unique geometric features. Several applications of CNTs to field emitters have been demonstrated in electron emission devices such as field emission display (FED), backlight unit (BLU), X-ray source, etc. In this study, we fabricated a CNT cathode by using filtration processes. First, an aqueous CNT solution was prepared by ultrasonically dispersing purified single-walled CNTs (SWCNTs) in deionized water with sodium dodecyl sulfate (SDS). The aqueous CNT solution in a milliliter or even several tens of micro-litters was filtered by an alumina membrane through the vacuum filtration, and an ultra-thin CNT film was formed onto the alumina membrane. Thereafter, the alumina membrane was solvated by acetone, and the floating CNT film was easily transferred to indium-tin-oxide (ITO) glass substrate in an area defined as 1 cm with a film mask. The CNT film was subjected to an activation process with an adhesive roller, erecting the CNTs up to serve as electron emitters. In order to measure their luminance characteristics, an ITO-coated glass substrate having phosphor was employed as an anode plate. Our field emitter array (FEA) was fairly transparent unlike conventional FEAs, which enabled light to emit not only through the anode frontside but also through the cathode backside, where luminace on the cathode backside was higher than that on the anode frontside. Futhermore, we added a reflecting metal layer to cathode or anode side to enhance the luminance of light passing through the other side. In one case, the metal layer was formed onto the bottom face of the cathode substrate and reflected the light back so that light passed only through the anode substrate. In the other case, the reflecting layer coated on the anode substrate made all light go only through the cathode substrate. Among the two cases, the latter showed higher luminance than the former. This study will discuss the morphologies and field emission characteristics of CNT emitters according to the experimental parameters in fabricating the lamps emitting light on the both sides or only on the either side.

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A Signal Readout System for CNT Sensor Arrays (CNT 센서 어레이를 위한 신호 검출 시스템)

  • Shin, Young-San;Wee, Jae-Kyung;Song, In-Chae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.9
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    • pp.31-39
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    • 2011
  • In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.